电气类外文翻译1-电气类(编辑修改稿)

电气类外文翻译1-电气类(编辑修改稿)内容摘要：

ge responding converters can exhibit very high errors when their input signals deviate from their precalibrated waveform。 the magnitude of the error depends on the type of waveform being measured. For example, if an average responding converter is calibrated to measure the rms value of sine wave voltages and then is used to measure either symmetrical square waves or dc voltages, the converter has a putational error 11% (of reading) higher than the true rms value (see Table 4). CALCULATING SETTLING TIME USING FIGURE 16 Figure 16 can be used to closely approximate the time required for the AD736 to settle when its input level is reduced in amplitude. The time required for the rms converter to settle is the difference between two times extracted from the graph (the initial time minus the final settling time). As an example, consider the following conditions: a 33 μF averaging capacitor, a 100 mV initial rms input level, and a final (reduced) 1 mV input level. From Figure 16, the initial settling time (where the 100 mV line intersects the 33 μF line) is approximately 80 ms. 5 The settling time corresponding to the new or final input level of 1 mV is approximately 8 seconds. Therefore, the time for the circuit to settle to its new value is 8 seconds minus 80 ms, which is seconds. Note that because of the smooth decay characteristic inherent with a capacitor/diode bination, this is the total settling time to the final value (that is, not the settling time to 1%, %, and so on, of the final value). In addition, this graph provides the worstcase settling time because the AD736 settles very quickly with increasing input levels. RMS MEASUREMENT—CHOOSING THE OPTIMUM VALUE FOR CAV Because the external averaging capacitor, CAV, holds the rectified input signal during rms putation, its value directly affects the accuracy of the rms measurement, especially at low frequencies. Furthermore, because the averaging capacitor appears across a diode in the rms core, the averaging time constant increases exponentially as the input signal is reduced. This means that as the input level decreases, errors due to nonideal averaging decrease, and the time required for the circuit to settle to the new rms level increases. Therefore, lower input levels allow the circuit to perform better (due to increased averaging) but increase the waiting time between measurements. Obviously, when selecting CAV, a tradeoff between putational accuracy and settling time is required. RAPID SETTLING TIMES VIA THE AVERAGE RESPONDING CONNECTION Because the average responding connection shown in Figure 19 does not use the CAV averaging capacitor, its settling time does not vary with the input signal level. It is determined solely by the RC time constant of CF and the internal 8 kΩ resistor in the output amplifier’s feedback path. 6 DC ERROR, OUTPUT RIPPLE, AND AVERAGING ERROR Figure 20 shows the typical output waveform of the AD736 with a sine wave input applied. As with all realworld devices, the ideal output of VOUT = VIN is never achieved exactly. Instead, the output contains both a dc and an ac error ponent. As shown in Figure 20, the dc error is the difference between the average of the output signal (when all the ripple in the output is removed by external filtering) and the ideal dc output. The dc error ponent is therefore set solely by the value of the averaging capacitor used. No amount of post filtering (that i。