电气电子专业毕业设计外文翻译--用spmc75的pdc定时器做bldc电机的速度检测-电气类(编辑修改稿)

电气电子专业毕业设计外文翻译--用spmc75的pdc定时器做bldc电机的速度检测-电气类(编辑修改稿)内容摘要：

o 127. The setting example is shown as blew. P_POS0_DectCtrl, = 2。 // Count on FCK/32 P_POS0_DectCtrl, = 1。 // Sample regularly P_POS0_DectCtrl, = 10。 // Sample 10 times P_POS0_DectCtrl, = 1。 // Enable position detection P_POS0_DectCtrl, = 100。 // Sample Delay Speed Calculation In order to obtain the exact parameters, the data must be filtered after captured. There are many filter algorithms, such as lowpass filter, moving average filter, median filter, average filter, limiting filtering, firstorder filter, moving average filtering, etc. In general, the data can be considered valid after processed by these filters. Then the speed can be calculated by substituting these parameters data in the formula. Assume Fcap is PDC capture clock frequency。 p is the polepair of BLDC rotor。 TCNT is cleared every m P_POSx_DectData (x = 0, 1) changes, that is, TCNT is cleared at 外文翻译（原文） 9 every *3m rad rotation (m=1, 3, 6), and the position data is Ncap Since: ddt (Formula 1 1) and d = *3m , Ncapdt Fcap Since electrical degree = p x mechanical rotation then the mechanical angular velocity is p  (Formula 1 2) with the unit of rad/min. Take n as the indicator. So: 260 30nn  rad/min (Formula 1 3) n summarize: 6 0 * * 1 0 * *3 * 2 * * *F c a p m F c a p mn N c a p p N c a p p rpm (Formula 1 4) From the formula above, we can obverse that n is related to Fcap, m, Ncap and p (that is a constant when BLDC is selected) . Suppose there is a BLDC with 2 polepair, 4000rpm rated speed. We will show you how to set the parameters of Fcap and m. When m= 1, TCNT is cleared every time P_POSx_DectData (x = 0, 1) changes, , that is, TCNT is cleared for once every 60 electrical degree rotation of BLDC. With a certain clock frequency, the motor rotation speed can be calculated by the Formula 1 4 at the highest speed when Ncap is 1 and the lowest speed when Ncap is 0xffff. Table 12 Motor Speed VS Clock Frequency Fcap n FCK/1 FCK/4 FCK/16 FCK/64 FCK/256 FCK/1024 Nmax (rpm) 120M 30M 1875K 468750 Nmin (rpm) 1831 ＠ When m= 3, TCNT is cleared for once every 3 times P_POSx_DectData (x = 0, 1) 外文翻译（原文） 10 changes, that is, TCNT is cleared every 180 electrical degree rotation of BLDC. From the Formula 1 4, we can see that the measurable motor speed when m= 3 is three times higher than that when m= 1, provided that other parameters are the same. ＠ When m= 6, TCNT is cleared every 6 times P_POSx_DectData (x = 0, 1) changes, that is, TCNT is cleared every 360 electrical degree rotation of BLDC. From the Formula 1 4, we can see that the measurable motor speed when m= 6 is six times higher than that when m= 1, provides that other parameters are the same. Above all, it is better to set m= 1 to ensure the veracity of positions. Since the highest speed can be applied, it is important to select the lowest speed. Assume the lowest measure speed is 200 rpm, we can set Fcap as FCK/16, FCK/64, FCK/256 or FCK/1024. FCK/16 is remended to be selected for higher veracity. Noise Immunity Through programming the bit value of SPLCNT (sampling count select) and SPDLY (sampling delay) in P_POSx_DectCtrl(x = 0, 1), users could avoid the erroneous detection due to noise that occurs immediately after PWM output turns on. It can ensure the correctness of speed measurement and phase mutation in BLDC . The valid settings are from 1 to 15 times. Note that count 0 and 1 are both assumed to be one time. These bits select the sampling count for the valid external position detection signals. The position signals must be sampled continuously match as many times as the sampling count set, for the position signals to be considered valid. Then the sharp pulse can be filtered by this method. SPLCK selects the sampling clock. Figure 12 shows the sampling counting and Figure 13 shows the noise immunity pulse. Figure 12 Sampling Counting 0 1 2 3 4 5 6 7 8 9 10 Hall3 Hall2 Hall1 SPLCK … 外文翻译（原文） 11 Figure 13 Noise Immunity Pulse See Figure 12 , the SPLCNT setting is 10. When sampling the position signal with the frequency that SPLCK selected, a hightolow transition occurs in hall3 at 0 to1 counting. Then sample the hall signal for ten executive times. If they are all of the same value, the hall signal can be considered valid. When SPLCNT setting is 10, a hightolow transition occurs in hall3 at the first counting, while a lowtohigh transition occurs at the fourth counting. Then reset the counter, sample hall3 for ten executive times. If they are all of the same value, the position signals can be considered as 011b still. By this way, a sharp pulse occurring in the signals can be filtered, which prevents the position signals from being disturbed. So the position signal will not be sampled if it varies quicker than the setting of SPLCK/SPLCNT does (note that count 0 and 1 are assumed to be one time). 2 Software Design Software Description This application note is designed for motor speed measurement when driving BLDC, which is performed by PDC position detection change interrupt. Source File File Name Function Type Main System initialization and motor detection (or performed by ISR) C ISR Position detection change input and speed calculation C Hall3 Hall2 Hall1 …… … 0 1 2 3 4 5 6 外文翻译（原文） 12 Spmc75 _SPDET_V100 The key function for speed calculation lib DMC munication function lib DMC Interface Speed1_No。