电梯语音报站器外文翻译(编辑修改稿)

电梯语音报站器外文翻译(编辑修改稿)内容摘要：

end of the memory. EOM logo only in the playback was detected in the internal EOM logo, the status bit is set to 1. Row address clock ( RAC ) open drain outputs. Each of the RAC cycle of said ISD memory operation carried out a row ( in the ISD4004 series Memory total of 2400 lines ). The signal 175ms to maintain a high level, low level25ms. Fast forward mode, the s is high, u s low. The terminal can be used for storage management technology. External clock ( XCLK ) the end has an internal pulldown element. Chip sampling clock in the factory before calibration, error in the +1%. Commercial grade chip in the temperature and voltage range, frequency variation in +%. Industrial grade chip in the temperature and voltage range, frequency variation in the 6 / +4%, then remend the use of regulated power supply. If greater accuracy is required, from the end of the external clock input ( as listed in the table ). Due to internal antialiasing smoothing filter is set, so the above remended clock frequency should not change. Input clock duty cycle be of no great importance, due to internal firstly, frequency divider. In no ground clock, this must end grounding. Automatic squelch ( AMCAP ) when the recording signal level drops to internally set a threshold, automatically mute function so that the signal is weak, which helps to feed without the noise signal ( mute ). Usually the end of grounding capacitance of 1mF, constitute the internal signal peak value detection circuit part. Detection of the peak level and internal set threshold for parison, automatic muting function turning point. Large signal, automatic squelch circuit without attenuation, attenuation of6dB mute. The capacitor of the 1mF also affect automatic squelch circuit for signal amplitude response speed. The terminating VCCA disable automatic squelch. SPI (serial peripheral interface ) ISD4004 to work with SPI serial interface. The SPI protocol is a synchronous serial data transmission protocol, protocol assumes that the microcontroller SPI shift register on the falling edge of SCLK action, so as to ISD4004, the clock stop rising along the latch pins of the MOSI data, the falling edge sends the data to the MISO pin. The specific content of the agreement for: 1 all serial data transmission begins at SS falling edge. during transmission must be maintained as low level, in the two instruction is maintained at a high level. 3data at the rising edge of the clock moved, at the falling edge out. goes low, the input mands and addresses, ISD to start recording operation. The 5 instruction format (8control code ) is a plus (16 bits of the address code ). any operations (including fastforward) if EOM or OVF, is to generate an interrupt, the interrupt status in the next SPI the beginning of the cycle is cleared. 7 the use of reading instruction so that the interrupt state displacement of ISD occurs on the MISO pin, control and address data should also be simultaneously from the MOSI terminal moving. Therefore attention should be paid to whether the data and devices are patible with operation current. Of course, is also allowed in a SPI cycle, while performing a read state and start a new operation (., new immigrant data and devices the operation can be inpatible). 8all the operations in a running position (RUN ) set to 1when begin, placing0at the end of. 9all instructions are in the SS rising start execution. ( a ) the information fast forward The user does not need to know the exact address information, can fastforward through a piece of information. Fast forward playba。