外文翻译--版图中常见的几个失效机制(编辑修改稿)

外文翻译--版图中常见的几个失效机制(编辑修改稿)内容摘要：

harge across its entire surface and injects this charge through the thin gate oxide. The vulnerability of a given geometry to the antenna effect therefore depends upon the ratio of the total area to the active gate area beneath it. The larger this areal antenna ratio, the greater the risk of plasmainduced damage. Most processes define a maximum allowed areal antenna ratio for poly。 a typical value is 500. Each conductor layer is vulnerable to the antenna effect during etching and ash, so each layer has its own peripheral and areal antenna ratios. Consider the case of metal2. Near the end of the etch process, the individual metal2 geometries bee separated from one anther. However, these geometries may be connected together through lower conductor layers. Therefore, the antenna effect cannot be evaluated on a geometrybygeometry basis. Instead, one must define collections of electrically connected geometries called nodes. During the metal2 etch, each node collects charge proportional to the metal2 periphery exposed to the plasma and injects this charge through the active gate beneath poly geometries forming part of the node. Therefroe, the metal2 peripheral antenna ratio of a node equals the total metal2 periphery of the node divided by the active gate beneath the poly geometries of the node. Similarly, the evaluation of ash damage depends upon the metal2 areal antenna ratio, defined as the total metal2 area of a node divided by the active gate area beneath the poly geometries of the node. A great deal of effort has been expended to understand the relationship between antenna ratios and gate dielectric damage, but much remains uncertain. Some researchers have uncovered evidence that PMOS gate oxides are considerably more sensitive to plasmainduced damage than NMOS gate oxides. Other researchers have shown that oxide isolation greatly reduces plasmainduced damage, presumably by limiting the current that can flow through any given area of gate oxide. Preventative Measures Any node whose antenna ratio exceeds specifications must be reworked. The exact techniques employed depend upon which layer is involved. In the case of polysilicon, the ratio can be reduced by inserting metal jumpers. Consider the case shown in Figure. This circuit contains a very long poly lead that crosses a minimumsize MOS transistor M1. The antenna ratios of this poly geometry could clearly bee very large. If, however, a short metal jumper is inserted in the poly lead next to the transistor, then the single poly geometry now bees two separate geometries. The geometry on the left (connecting to the gate of transistor M1) has relatively small antenna ratios. The geometry on the right (connecting to the source/drain of transistor M2) has zero antenna ratios because no gate oxide lies beneath it. Therefore, the addition of the metal jumper has eliminated any potential problem. 1M1MoatNM Poly 1Metal 2M2MNMo at o x i d e g a t e eV u l a n e r a b lj u m p e r 1M e t a l Figure 3 Metal layers are somewhat more difficult to evaluate because metal nodes can connect to diffusions that leak away the charge before it damages gate oxides. For processes that employ gate oxides thicker than about 400Ǻ, the source/drain junctions of the MOS transistors will typically avalanche before the gate oxides can be damaged. In such cases, any node that connects to a source/drain diffusion can generally be ignored when puting antenna ratios. If a metal node is found to have an excessive antenna ratio, the problem can be eliminated either by placing a jumper on a higher metal layer (as discussed previously in connection with poly), or by connecting a source/drain diffusion to the node. If the circuit dose not include a transistor connected to the node, then a small structure called a leaker can be attached instead. Figure show shows examples of NSD/Pepi leaker is preferred. This structure is essentially a diode whose anode is connected to the metal node and whose cathode is connected to the substrate. If the voltage on the node drops below the substrate potential, then the leaker will forwardbias and clamp the voltage. If the voltage on the node rises above substrate potential, then the NSD/Pepi junction will avalanche before the thick oxide is damaged. N M o a tC o n t a c twellN PM oatC o n t a c t Figure 4 Leakers for thinoxide processes are somewhat more problematic. The avalanche voltage of an NSD/Pepi junction cannot be relied upon to protect a gate oxide much thinner than 400Ǻ. Experience has shown that nodes in thinoxide processes can be protected by a bination of NSD/Pepi and PSD/Nwell leakers. The NSD/Pepi leaker will forwardbias if the node drops below substrate potential. The PSD/Nwell leaker will forwardbias if the note rises above the Nwell potential, but the reversebiased Nwell/Pepi junction prevents currents from flowing through this structure during normal operation. During reactive ion etching, the light from the plasma reaction shines down on the wafer. This light encourages photogeneration within the depletion region of the charge injected onto the Nwell. In order for the Nwell/Pepi leaker to properly function, at least a portion of its periphery should remain uncovered by metal to a distance of at least 510μm outside of drawn Nwell. Whenever leakers are inserted, the circuit designer should be informed of their presence so that their effect upon circuit operation can be evaluated. In most cases, the leakers will not interfere with the circuit, but it is impossible to make blanket statements about what might or might not interfere with analog circuits. MinorityCarrier Injection Junction isolation relies on reversebiased junctions to block unwanted current flow. The electric fie。