外文翻译---基于c51兼容微处理器单片机的pwm控制器设计-单片机(编辑修改稿)

外文翻译---基于c51兼容微处理器单片机的pwm控制器设计-单片机(编辑修改稿)内容摘要：

se frequency can be divided by 4 times or 12 times through setting the value of T3M for PWM0 or T4M for PWM1 in the special register PWMCON as shown in . To PWM0 generator, the clock to 16bit counter will be predivided by 4 times by default when T3M is set to zero. And the clock will be divided by 12 times when T3M is set to 1. This is also true for PWM1. The other bits in PWMCON are explained in detail in Table 1. Fig .4 Bit Mapping of PWMCON Table 1: The Bit Definition in PWMCON 大连交通大学 2020 届本科生毕业设计外文翻译 5 Channelselect logic The follow Fig. 5 shows the channelselect logic which is useful in Complementary Mode. From this diagram, it is clear to know that signal CP and CPWM control the source of PWMH and PWML. And the details about the two control signals will be discussed in the section 3, and the architecture of deadtime generator will also be discussed in section 5 for the continuity of Complementary Mode. Fig. 5 Diagram of Channelselect Logic Operation Mode and Simulation Results The design has two operation modes: Independent Mode and Complimentary Mode. By setting the corresponding bit CPWM in register PWMCON shown in user can select one of the two operation modes. When CPWM is set to zero, PWM module will work in Independent Mode, whereas, PWM module will work in Complimentary Mode. In the following of this section, the two operation mode will be explained respectively in detail and the simulation results of the PWM module from the Synoposys VCS EDA platform which 大连交通大学 2020 届本科生毕业设计外文翻译 6 verify the design will also be shown. Independent PWM Output Mode An Independent PWM Output mode is useful for driving loads such as the one shown in Figure 6. A particular PWM output is in the Independent Output mode when the corresponding CP bit in the PWMCON register is set to this case, twochannel PWM outputs are independent of each other. The signal on pin PWM0/PWMH is from PWM0 generator, and the signal on pin PWM1/PWML is from PWM0 generator. The separate case is achieved by the channelselect logic shown in Fig. 6. The PWM I/O pins are set to independent mode by default upon advice reset. The deadtime generator is disabled in the Independent mode. The simulation result is shown in Figure 6 as the following Tr4 and tr3 are run bits to PWM0 and PWM1, respectively. Actually, from this diagram, Pin P1[5]/ P1[4] of MCU is used for PWMH/ PWML or normal I/O ,alternatively. Fig6 the Waveform of PWM Outputs in Independent Mode Complementary PWM Output Mode The Complementary Output mode is used to drive inverter loads similar to the one shown in Figure 7. This inverter topology is typical for DC applications. In Complementary Output Mode, the pair of PWM outputs cannot be active simultaneously. The PWM channel and output pin pair are internally configured through channelselect logic as shown in Figure7. A deadtime may be optionally inserted during device switching where both outputs are inactive for a short period. 大连交通大学 2020 届本科生毕业设计外文翻译。