外文翻译---借助dds的精密频率的一种替代方法(编辑修改稿)

外文翻译---借助dds的精密频率的一种替代方法(编辑修改稿)内容摘要：

trary, when the second counter (2) counts two rising edges of the DDS output within a period of the unknown frequency it resets the RS flipflop39。 s output. This action decreases the frequency of the DDS. At a first glance one could think that the synthesized frequency could reach the measured one (fin) and then the operation of the counter stops. Unfortunately this is not the case. A dynamic mechanism takes place instead. The circuit needs some time to realize the correct frequency relation. We will refer to this time as hysteresis. Hysteresis depends on the initial timing relation of the DDS output and on the unknown frequency. Initially, during the hysteresis period, the indication regarding the larger frequency is ambiguous . it can be erroneous. The ambiguity settles when two rising edges of the higher frequency waveform occur during one period of the lower one. If we consider the case of the DDS frequency to be equal to the unknown one, we will find that the parator39。 s output will toggle, indicating alternatively that the DDS frequency is higher or lower than the unknown. This is actually an acceptable and expected condition, because (as in a voltage parator) an equality indication could not exist. In our case this is not a problem because the circuit is embedded in a closed loop. The loop will act in a manner that after some short time, the hysteresis, the situation will be reversed and so on. The duration of hysteresis is variable. This situation is controlled, as will be explained later. Although an analog implementation of the frequency parator would look more robust to noise we insisted to the digital implementation for three reasons: ease of implementation in VLSI or Programmable Logic Devices (PLDs) with no need of analog ponents, wide frequency range of operation and shorter response time. Interaction between frequency parator and digital synthesizer After the successive approximation of the unknown frequency the Frequency Comparator realizes that the synthesized frequency is higher (lower) than the unknown one and produces a logic 0 (1) at the output which mands the up/down counter to count in the down (up) direction. As previously mentioned, the output of this counter is considered to be the FSW to the DDS stage. In the case when the DDS frequency was initially lower, the synthesized frequency will increase progressively to reach the unknown one. This will not be realized by the frequency parator and the synthesized frequency will keep on increasing for some clock cycles, until the parator detects the correct relation of it39。 s two input frequencies, the unknown one and the DDS output. The same phenomenon will be observed for the opposite (decreasing) case also. This is due to hysteresis that was mentioned earlier. When DDS output (fDDS) has approached fin, due to hysteresis, no specific frequency is synthesized. Instead, it swings between f1 and f2, where f1 and f2 are the two extreme values of the frequency swing lying symmetrically around fin. The DDS output can be considered as a frequency modulated carrier by a triangular waveform. The triangular waveform is the analog representation of the FSW applied to the DDS. lower trace shows a typical output of the Frequency Comparator. In the same figure, upper trace, is shown in analog form the FSW variation as it is trying to approach the correct value. This waveform has been captured using an auxiliary hardware circuit: A digitaltoanalog converter (DAC) was connected to the output of the U/D counter (MSBs) in order to study the operation. This DAC is not shown in the block diagram of the circuit. Stated differently, the lower trace is the U/D mand (input) to the counter while the upper trace is a hypothetical frequency modulating waveform. It is obvious that the term hypothetical is used because there is not such a waveform available somewhere in the circuit (except for the auxiliary DAC). Instead, its numerical equivalent exists. The magnitude of the slope of the elements of the triangular waveform is constant for constant input frequency and depends on the clock of the U/D counter (horizontal axis) and the voltage reference of the DAC (vertical axis). This。