外文文献翻译----微控制器(编辑修改稿)

外文文献翻译----微控制器(编辑修改稿)内容摘要：

allows operation without external oscillator ponents. The RC oscillator option is selectable and fine tunable. Fast switching between the internal RC oscillator and any oscillator source provides optimal support of minimal power active mode with fast switching to maximum performance. V to V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or driven to V). 44pin packages with 40 I/O pins minimum while using onchip oscillator and reset options. Port 5 has high current sourcing/sinking (20 mA) for all Port 5 pins. All other port pins have high sinking capability (20 mA). A maximum limit is specified for the entire chip. Watchdog timer with separate onchip oscillator, requiring no external ponents. The watchdog prescaler is selectable from eight values. Additional features A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns for all instructions except multiply and divide when executing at 18 MHz. This is six times the performance of the standard 80C51 running at the same clock frequency. A lower clock frequency for the same performance results in power savings and reduced EMI. Serial flash InCircuit Programming (ICP) allows simple production coding with mercial EPROM programmers. Flash security bits prevent reading of sensitive application programs. Serial flash InSystem Programming (ISP) allows coding while the device is mounted in the end application. InApplication Programming (IAP) of the flash code memory. This allows changing the code in a running application. Low voltage (brownout) detect allows a graceful system shutdown when power fails. May optionally be configured as an interrupt. Idle and two different powerdown reduced power modes. Improved wakeup from Powerdown mode (a LOW interrupt input starts execution). Typical powerdown current is 1 mA (total powerdown with voltage parators disabled). ActiveLOW reset input can be driven by any internal reset. Onchip poweron reset allows operation without external reset ponents. A reset counter and reset glitch suppression circuitry prevent spurious and inplete resets. A software。