基于虚拟仪器的可重构逻辑外文翻译(编辑修改稿)

基于虚拟仪器的可重构逻辑外文翻译(编辑修改稿)内容摘要：

neric one. Therefore, our proposal is focused on the enhancement of virtual instruments by the replacement of the generic hardware with a reconfigurable data acquisition system, as it is shown in Figure 1. By this way, some data process can be implemented by hardware reducing the data flow to/from the puter and rising the maximum sample rate. The benefits of virtual instruments based on reconfigurable logic are the following: The bandwidth of the instruments can be increased implementing the more time critical algorithms by hardware. The input/output capacity can be reconfigured according to the application. In special, 中原工学院信息商务学院外文翻译 11 FPGAs devices are characterized by a great number of input/output pins providing virtual instrument with the capacity to observe and control a wide number of signals. The puter interface can be reconfigured according to the available resources (Plugamp。 Play peripherals). Different instruments can share software and hardware design modules increasing their reusability. 2. The position and classification of virtual instruments Virtual instrument system mainly consists of puters, hardware board,software and accessories. Users can request the flexibility to build their own testing equipment. The core of virtual instrument is software, which is mainly provided by the hardware driver, application programming software etc. It can plete all the test requirements. The current development environment mainly into two categories:(1) text language。 (2) graphics language. As the graphic language developed by convenience weled by the majority of engineers. There are not many trained in puter language engineers able to master the development of virtual instrument technology and applied to engineering practice in a relatively short period of time. Virtual instrument is essentially an open structure which to provide signal processing, storage and display functions by generalpurpose puter, digital signal processors, or other CPU. To achieve instrument functions from data acquisition boards, GP IB or VXI bus interface board for signal acquisition and control. According to its different ways of using the bus can be divided into the following types: (1) PC Bus plugin cardbased virtual instrument (2) parallel port virtual instruments (3) the way of GB IB bus virtual machines (4) VXI bus mode Virtual Instrument (5) PXI bus mode virtual instruments 3. Reconfigurable Data Acquisitions Systems We propose the implementation of a reconfigurable data acquisition system using FPGAs. This system operates like a reconfigurable coprocessor oriented to the capture, generation and analysis of digital signals. The bination of this hardware with a general purpose puter results in a reconfigurable virtual instrumentation system where the end user determines the software and hardware resources required for each particular application. General Description 中原工学院信息商务学院外文翻译 12 The more essential blocks of a data acquisition system are represented in Figure 2. As an application oriented system, most of these modules must be scalable (increasing or decreasing the number of input/output pins) according to different applications. For example, the capacity of the acquisition memory varies with the requirements of the instrument. At the same time, if the device provides with enough resources, several instruments can be active simultaneously. In this case, some blocks of the structure shown in Figure 2 must be multiplied accordingly while others can be shared among instruments. For example, an unique puter interface block multiplexed in time is generally more efficient because less input/output pins are dedicated to the munication tasks. In the puter side, the software is dedicated to the storage and visualization of data, and also to the configuration and control of the hardware. The first tasks are implemented at application level and take advantage of multitask operating syste ms and their advanced graphic interfaces. The second tasks are mainly implemented as extensions of the operative systems and in this way they are closely linked to the hardware. The blocks represented in Figure 2 are briefly described in the next sections. Also, the characteristics of the configurable devices (SRAM FPGAs) required for the implementation of these blocks are indicated. Input/Output Modules The input/outputs modules conform the interface with the real world. The input/output blocks of the reconfigurable device must be bidirectional, with tristate capability and internal registers for faster capture rates. Acquisition Control Block The data capture is usually synchronized with some external or internal events and this task is developed by the acquisition control module. As a consequence, the routing of this control signals to the input/output blocks and to the internal logic bees very important. An architecture with several low skew and great fanout distribution works is mandatory for this purposes. At the same time, several inputs and outputs usually share mon control signal so a device with a peripheral bus carrying control signals is suitable for this application. Timing Blocks The timing blocks (oscilator, timers and counters) provides internal control signals to 中原工学院信息商务学院外文翻译 13 the data acquisition system. Special attention was dedicated to the design of counters in order to reach maximum operating frequencies. Memory Blocks The memory blocks operate as a temporary storage of the acquired/generated。