基于单片机的十字路口交通灯控制器的设计外文翻译-单片机(编辑修改稿)

基于单片机的十字路口交通灯控制器的设计外文翻译-单片机(编辑修改稿)内容摘要：

T89C51 has the following standard function: 8k bytes Flash, 256 bytes RAM, 32bit I/O mouth line, the watchdog timer, two data pointer, three 16 timer/counter, a 6 vector level 2 interrupt structure, fullduplex serial port, piece inside crystals timely clock circuit. In addition, AT89C51 can drop to 0Hz static logic operation, support two software can choose power saving mode. Idle mode, the CPU to stop working, allowing the RAM, timer/counter, serial ports, interruption continue to work. Power lost protection mode, RAM content being saved, has been frozen, microcontroller all work stop, until the next interruption or hardware reset so far. As shown in figure 1 for the AT89C51 pins allotment.RST/Vpd9(RXD)(TXD)(INT0)(INT1)(T0)(T1)(WR)(RD)XTAL218XTAL119END20 P20(A8) 21P21(A9) 22P22(A10) 23P23(A11) 24P24(A12) 25P25(A13) 26P26(A14) 27P27(A15) 28PSEN 29EA/Vpd 31ALE/PROG 30(AD7) 32(AD6) 33(AD5) 34(AD4) 35(AD3) 36(AD2) 37(AD1) 38(AD0) 39VCC 40Figure 1 the AT89C51 pins allotment(2) interrupt introductionAT89C51 has six interrupt sources: two external interruption, (and), three timer interrupt (timer 0, 1, 2) and a serial interrupts. Each interrupt source can be passed buy bits or remove IE the relevant special register interrupt allow control bit respectively make effective or invalid interrupt source. IE also includes an interrupt allow total control bit EA, it can be a ban all interrupts. IE. Six is not available. For AT89C51, IE. 5 bits are also not be used. User software should not give these bits write 1. They AT89 series for new product reserved. Timer 2 can be TF2 and the T2CON registers EXF2 or 14logical triggered. Program into an interrupt service, the sign bit can be improved by hardware qing 0. In fact, the interrupt service routine must determine whether TF2 or EXF2 activation disruption, the sign bit must also by software qing 0. Timer 0 and 1 mark a timer TF0 and TF1 has been presented in the cycle count overflow S5P2 074 bits. Their value until the next cycle was circuit capture down. However, the timer 2 marks a TF2 in count overflow of the cycle of S2P2 074 bits, in the same cycle was circuit capture down(3) external clock driving characteristicssymbols parameters minimum The maximum unit1/TCLCL OscillatorFrequency 0 24 MHzTCLCL Clock Period nsTCHCX High Time 15 nsTCLCX Low Time 15 nsTCLCH Rise Time 20 nsTCHCL Fall Time 20 nsTable 1(4) leisure and power lost pattern external pins statemode Program memory ALE ^psen Port0 Port1Port2Port3idle internal 1 1 data data data DataIdle External 1 1 float Data data DataPower down Internal 0 0 Data Data Data DataPower down External 0 0 float data Data dataTable 2 About 8255 chip features:(1)A parallel input/output LSI chips, efficacy of I/O devices, but as CPU bus and peripheral interface.(2)It has 24 programmable Settings of I/O mouth, even three groups of 8 bits I/O 15mouth to mouth, PB mouth and PA PC mouth. They are divided into two groups 12 I/O mouth, A group including port A and C mouth (high four, PC4 ~ PC7), including group B and C port B mouth (low four, PC0 ~ PC3). A group can be set to give basic I/O mouth, flash control (STROBE) I/O flash controlled, twoway I/O3 modes, Group B can only set to basic I/O or flash controlled the I/O, and these two modes of operation mode entirely by controlling registers control word decision.2. 8255 pins efficacy: (1). RESET: RESET input lines, when the input outside at high levels, all internal registers (including control registers) were removed, all I/O ports are denoting input methods. (2). CS: chip choose a standard lamp line 1, when the input pins for low levels, namely/CS = 0, said chip is selected, allow 8255 and CPU for munications, / CS = 1, 8255 cannot with CPU do data transmission.(3). RD: read a standard lamp line 1, when the input pins for low levels, namely/RD = 0 and/CS = 0, allow 8255 through the data bus to the CPU to send data or state information, namely the CPU 8255 read from the information or data. (4). The WR: write a standard lights, when the input pins for low levels, namely/WR = 0 and/CS = 0, allows the CPU will data or control word write 8255. (5). D7: three states D0 ~ twoway data bus, 8255 and CPU data transmission channel, when the CPU execution input/output instruction, through its realization 8 bits of data read/write operation, control characters and status information transmitted through the data bus.(6). PA0 ~ PA7: port A input and output lines, A 8 bits of data output latches/buffers, an 8 bits of data input latches.(7). PB0 ~ PB7: port B input and output lines, a 8 bits of I/O latches, an 8 bits of input and output buffer. (8). PC0 ~ PC7: port C input and output lines, a 8 bits of data output latches/buffers, an 8 bits of data input buffer. Port C can through the way of working setting into two four ports, every 4 digit port contains A 4 digit latches, respectively with the port A and port B cooperate to use, can be used as control standard lights output or state standard 16lights input ports. (9). A0, A1: address selection line, used to select the PA 8255 mouth, PB mouth, PC mouth and controlling registers. When A0=0, A1= 0, PA mouth be chosen。 When A0=0, A1 = 1, PB mouth be chosen。 When A0=0, A1 = 1, PC mouth be chosen。 When A0=1, A1= 1, control register is selected. Concerning seven section LED display introduction Through light emitting diode chip appropriate link (including series and parallel) and appropriate optical structure. May constitute a luminous display lightemitting segments。