差分信号differentialsignaling(ppt69)英文-经营管理(编辑修改稿)

差分信号differentialsignaling(ppt69)英文-经营管理(编辑修改稿)内容摘要：

tial Signaling 下载 Example of Simple CML Differential Behavioral Circuit Vcc Vss I_source r_termn, C_term r_termp, C_term 0 10 20 3001D a t a P u l s e s0 10 20 3001D a t a W a v e sw a v e t( ) 1 ep u l s e t( ) 3 p e rnsW a v e p t( )W a v e p t( ) 1 r _ t e r m n b a la n c e p W a v e n t td( ) 1W a v e n t td( ) r _ t e r m n b a la n c e nPositive Terminal Negative Terminal This exponent determines wave shape This switch time offset Balance between for FET switch 27 12/4/2020 Differential Signaling 下载 Example of Sensitivities: I, balance, C Vcc I_source More prominent for faster edges 28 12/4/2020 Differential Signaling 下载 Example of Sensitivities: Slew, Skew, R Vcc I_source +/skew R/F slew 29 12/4/2020 Differential Signaling 下载 Serial Differential GHz transmission will have many UI’s of data in transit on the interconnect at any points in time. Hence it bees useful to think of this as serial data transmission. Often multiple single channels are ganged in parallel to achieve even higher data throughput. 30 12/4/2020 Differential Signaling 下载 AC coupling issues Series capacitors can build up charge difference between differential terminals for the following reasons. Unequal numbers off zero and ones Duty cycle (UI) distortion. The solution is to use a data code that is “DC” balanced. 8B10B (8 bit 10 bit) with disparity is one such code Tight UI control is a basic requirement for keeping the signal eye open 31 12/4/2020 Differential Signaling 下载 Eye Diagram  The eye diagram is a convenient way to represent what a receiver will see as well as specifying characteristics of a transmitter.  The eye diagram maps all UI intervals on top of one and other.  The opening in eye diagram is measure of signal quality.  This is the simplest type of eye diagram. The are other form which we will discuss later Eye Diagram 32 12/4/2020 Differential Signaling 下载 Creating eye diagram Plot periodic voltage time ramps (saw tooth waves) on x verses the voltage wave on Y.  Can be done with Avanwaves expression calculator and can be saved in a configuration file. 33 12/4/2020 Differential Signaling 下载 Create ramp with expression builder Start of relative eye position Time of eye start Unit Interval 34 12/4/2020 Differential Signaling 下载 Copy Ramp to X Axis Use middle button to drag ramp to Current XAxis 35 12/4/2020 Differential Signaling 下载 Voltage and period volttime ramp 36 12/4/2020 Differential Signaling 下载 Clocking  The one thing omitted in the suggests in the previous slides on eye diagrams was the “chop” frequency.  We assumed it was UI. This is simple for simulation. Time marches along and all signals start out synchronized in time. This is not true for real measurement since edges will significantly jitter and make it difficult to determinate where the exact UI is positioned.  Presently, there are basically two forms of GHz+ clocking Embedded clocking Forwarded clocking 37 12/4/2020 Differential Signaling 下载 Embedded clocking  This what is used in Fiber Channel, Gigabit Ether, PCI Express, Infiniband, SATA, USB, etc.  The clock is extracted from the data There is requirement that data transitions are at a minimum rate. 8B/10B guarantees this. We discuss this in more detail later. A phase interpolator is normally used to extract the clock from the data. We discussed the phase interpolator in the clocking class. The phase interpolator is tied to the PCI Expresslike jitter spec: Median and Jitter outlier. 38 12/4/2020 Differential Signaling 下载 Jitter Median and Outlier Spec  Eye opening is defined from a stable UI.  Jitter median used to determine a stable UI It is used as a reference to determine eye opening  Jitter Outlier is used to guarantee limits of operation Jitter Median Jitter outlier Eye diagram UI 39 12/4/2020 Differential Signaling 下载 Forwarded Clocking  The Tx clock is sourced and received down stream. The clock is a Tx data buffer synchronized with the Tx data bits.  A synchronization or training sequence on a data line is used to adjust the receiver clock so that it is in phase synchronization with the data.  The caveat is that the actual data clock lags the real data by a few cycles.  The whole idea is that the jitter introduced over these cycles would be smaller than the jitter associated with two the PLLs used to provide base clocks for an embedded clock design. 40 12/4/2020 Differential Signaling 下载 Aspects of AC coupling  We will explore issues with AC coupling with a simulation example.  First we will create a simple CML differential model  Next we will tie it to a differential transmission line and a terminator.  Assignment 7 is to reproduce these effects with a HSPICE program. The output Avanwaves with a power point story summary what you will hand in.  The basis for our work will be last semesters deck 41 12/4/2020 Differential Signaling 下载 Behavioral Data Model – Example 12 bit of repeating data 010101 001001 … v(t) data UI = 500 ps Tr=Tf=100ps ))*((1 tveRterm=50 Cterm= Vswing = 800 mV I=Vswing/(50||50)/2 Wave shape* * Refer to first course 42 12/4/2020 Differential Signaling 下载 AC coupled Differential Circuit 1 n H1 n H1 n H1 n H. 2 5 p f. 2 5 p f. 2 5 p f. 2 5 p f1 6 m a1 0 n1 0 n1 . 0 g H z0 /8 0 0 m VV c c+V C R+V C R50505050AC coupling caps are normally larger, but are scaled down to illustrate mon mode effects 43 12/4/2020 Di。