ibmpcat硬件架构与动作原理(ppt51)中英文-咨询报告(编辑修改稿)

ibmpcat硬件架构与动作原理(ppt51)中英文-咨询报告(编辑修改稿)内容摘要：

D A C K 31 3 . 1 4 . 2 9 D R Q 31 3 . 1 4 D A C K 11 3 . 1 4 . 2 9 D R Q 11 2 . 2 9 R E F R E S H 1 2 . 3 3 S Y S C L K1 3 . 1 4 . 2 9 I R Q 71 3 . 1 4 . 2 9 I R Q 61 3 . 1 4 . 2 9 I R Q 51 3 . 1 4 . 2 9 I R Q 41 3 . 1 4 . 2 9 I R Q 31 3 . 1 4 . D A C K 21 3 . 1 4 T C1 2 B A L E5 O S C 11 2 . 2 9 M E M C S 1 6 1 2 . 2 9 I O C S 1 6 1 3 . 1 4 . 2 9 I R Q 1 01 3 . 1 4 . 2 9 I R Q 1 11 3 . 1 4 . 2 9 I R Q 1 51 3 . 1 4 . 2 9 I R Q 1 21 3 . 1 4 . 2 9 I R Q 1 41 3 . 1 4 D A C K 01 3 . 1 4 . 2 9 D R Q 01 3 D A C K 51 3 . 2 9 D R Q 61 3 D A C K 61 3 D A C K 71 3 . 2 9 D R Q 71 3 . 2 9 D R Q 52 9 R M A S T E R I SA SL O T S17 KT9 System Block Diagram 18 NS87570 MS1535+ DC to DC Buck Converter Logicamp。 Delay circuit DNBSWON NBSWON SUSB SUSC SUSON MAINON VRON HWPG_POWER NPWROK NB_PWROK SB_PWROK CPU_PWRGD (1) RVCC (2) (3) (4) (5) (6) (7) PWR BUTTON KT9 Power On Block Diagram 19 System Start Steps (1) 1. Power ON/OFF Button PC87570(PCU) 2. PC87570 M1535+(South Bridge) 3. M1535+ PC87570 SUS Power(3VSUS、 5VSUS) 4. PC87570 Main Power(3V、 5V、 ) VHcore NBSWON SUSB/SUSC DNBSWON SUSON MAINON VRON20 • 1. When we push the Power Button, the signal NBSWON will be generated and send to the PCU(PC87570). • 2. As the PCU receives the NBSWON, it will send the DNBSWON to the south bridge(M1535+). • 3. Then the SB asserts SUSB and SUSC signals to the PCU. • 4. The PCU will send the SUSON, MAINON and –VRON for suspend power, main power and VHcore generating. System Start Steps (1) 21 PC87570 SUSON SC1470 PQ51/PQ16 PQ3/PQ55 12VS PQ8 PQ40 3VSUS 5VSUS PC87570 MAINON PQ61 PQ44 PQ50/PQ39 LP2996 PQ7/PQ57 3VAGP 12V VTT_DDR PQ8 PQ40 3V 5V SUSD MAIND PC87570 VRON HIP6301 VHcore 22 System Start Steps (2) HWPG 5. MAX1632 HWPGPOWER PC87570 6. PC87570 NPWROK D 5 0 R B 5 0 0NB_PWROK RS200MP (NB) Q8MMBT390421 3NB_PWROK U66 PWROK D 5 1 R B 5 0 0 7. SB_PWROK M1535+ Q58Q59 CPU_PWRGD Q12MMBT390421 3PWRGOOD CPU 23 System Start Steps (3) SYS_RST 8. M1535+ PCI_RST PCI_RST 9. NB_PCIRST RS200MP SB_PWROK U 5 27S H 08U537SH0812345U547SH0812345 PCIRST I/O Devices 10. RS200MP CPU_RST CPU ** CPU and all I/O devices have been reset. 24 System Start Steps (4) 11. CPU– Memory Code Read North Bridge Address (A31 ~ A3) : FFFF FFF0 12. North Bridge : CPU Command PCI Command CPU Address PCI Address 13. North Bridge – Memory Read South Bridge Address ( AD31 ~ AD0) : FFFF FFF0 14. South Bridge : PCI Command ISA Command PCI Address ISA Address 25 System Start Steps (4) 11. CPU will generate the first mand Memory Code Read to the North Bridge, and the Host address (A31 ~ A3) : FFFF FFF0. 12. When the NB receives the CPU mand and Host address, It will translate the CPU mand to PCI mand(Memory Read), and translate the Host Address to the PCI address(AD31~AD0):FFFF FFF0. 13. Then the NB sends the PCI mand and PCI address to the South Bridge via the PCI Bus. 14. AS the SB receives the PCI mand and PCI address, it will translate the PCI mand to the ISA mand(MEMR) and the PCI address to the ISA address(A19~A0):FFFFF. 26 System Start Steps (5) 15. South Bridge – MEMR System ROM Address ( SA17 ~ SA0 ): 1FFF0 16. ROM Data – ISA Data Bus South Bridge 17. South Bridge – PCI Data Bus North Bridge 18. North Bridge – Host Data Bus CPU 19. CPU: Decode and Execute (Go To Step 11 : Decode amp。 Execute) 27 System Start Steps (5) 15. THE SB will drive the MEMR mand to the System ROM and access the ROM address ( SA17 ~ SA0 ): 1FFF0 16. So the ROM Data will be transferred to South Bridge through the ISA Bus 17. And then through the PCI Bus, the South Bridge will send the PCI date to the North Bridge 18. At the last the North Bridge will send Host data to the CPU through the Host Bus. 19. After the CPU fetch the host data which is transferred from North Bridge, it begins to Decode amp。 Execute(Go To Step 11 : Decode amp。 Execute). 28 The first Execution Instruction in PC AT 1. CPU Address :: A31 ~A3 = FFFF FFF0 2. CPU :: CS: IP = F000:FFF0 FFFF0 3. ISA Address :: SA17 ~ SA0 = 1FFF0 4. ISA Data :: 1FFF0: EA 5B E0 00 F0 30 37 2F 1FFF8: 31 35 2F 39 39 00 FC 00 5. EA 5B E0 00 F0 = Long Jump F000:E05B 30 37 2F 31 35 2F 39 39 = 07/15/99 29 POST (PowerOn Self Test) Process POST tests and initializes the following : 1. The central processing unit ( CPU ) 2. The ROM BIOS ( checksum ) 3. The CMOS RAM 4. The Intel 8237 DMA Controller 5. The keyboar。