pec电子工程英语证书考试复习资料(编辑修改稿)

pec电子工程英语证书考试复习资料(编辑修改稿)内容摘要：

al EMI remedies involve the addition of extra ponents, metal shields, metal plans, or even redesigning the entire system. Synonym: radiofrequency interference. EMI/EMC Acronym for Electromagic Interference/Electromagic Control. equationbased model A model based on equations that describe the behavior of the device, or circuit, modeled. Most importantly, the output as a function of the input. ESD Acronym for ElectroStatic Discharge. A transfer of electric charge between bodies of different electrostatic potential in close proximity or through direct contact (ANSI – 1992). ESS Acronym for Environmental Stress Screening. eV Abbreviation for electronvolt. F F Symbol for Farad, measure of capacitance. f Abbreviation for frequency. FACT Acronym for Fairchild Advanced Cmos Technology, as in 74FACT245. FAST Acronym for Fairchild Advanced Schottky TTL, as in 74F245. FCT Acronym for Fast Cmos Technology, as in 74FCT245. FDTD Acronym for Finite Difference Time Domain modeling. FEA Acronym for Finite Element Analysis. FEM Acronym for Finite Element Method. Method of numerical putational electromagics. Essentially everybody does some form of this for field solvers, such as Tlines. FET Acronym for Field Effect Transistor. FFT Acronym for Fast Fourier Transform. FOM Acronym for Figure Of Merit. FPGA Acronym for field programmable gate array. functional modeling Modeling by the use of mathematical functions, algorithms and formulas. G G Symbol for giga, as in10+12 GaAs Acronym for Gallium Arsinide. GB or Gbit or GBIT Acronym for GigaBit. glue logic Small ICs that level shift and otherwise perform simple functions that enable large blocks of logic (ASICs, microprocessors, memories) to work together. Thus gluing them together. GND Acronym for GrouND. A reference connection monly connected to Earth, whose electric potential is usually equal to zero. ground bounce The transient rise or fall in voltage on a ground plane or ground pin from its ideal quiescent value of zero due switching currents on and off through impedance (mostly inductance) in the ground path. A similar effect on the power plane causes power bounce. The result is noise on the signal that can decrease signal to noise ratio in analog circuits or lead to false switching in digital circuits. GTL Acronym for Gunning Transceiver Logic, as in 74GTL245. GTLP Acronym for Gunning Transceiver Logic Plus, as in 74GTLP245. guardbanding The practice of adding safety margin, or extra safety margin, to specification limits or population distributions. H H Abbreviation for Henry, the unit of inductance. HALT Acronym for Highly Accelerated Life Test. HASS Acronym for Highly Accelerated Stress Screening. HC Acronym for High speed Cmos, as in 74HC245. HCT Acronym for High speed Cmos with TTL thresholds, as in 74HCT245. HDL Acronym Hardware Description Language. One of several specialized highlevel languages used by semiconductor designers to describe the features and functionality of chips and systems prior to handoff to the IC layout process. HDL descriptions are used in both the design implementation and verification flows. Currently, the two standard HDLs in use worldwide are VerilogHDL and VHDL. Several proprietary HDLs also exist, mainly for describing logic that is targeted for vendorspecific programmable logic devices. highspeed digital design The design of digital circuits relative to their analog behavior. Particularly, where the fast switching edge rates used cause transmission line effects to bee significant. hole A gap left in the covalent bond when a valence electron gains sufficient energy to jump to the conduction band. HSDD Acronym for HighSpeed Digital Design. HSDD, as used in this book, applies to both active and passive circuit elements. HSTL Acronym for High Speed Transceiver Logic. HTL Acronym for High Threshold Logic. HTTL Acronym for High power TransistortoTransistor Logic. Hz Symbol for Hertz, as in cycles per second. I I/O Symbol for Input/Output. IBIS Acronym for Input/output Buffer Information Specification. IBIS model A data file produced in conformance with the IBIS Specification. The IBIS file, or model, provides necessary data for a simulator to predict the analog behavior of digital circuits. IBIS quality levels Four levels of increasing quality as defined in the IBIS quality checklist. IBIS rise time Rise time based on the IBIS [Ramp] specification of 20% to 80% of 0 Volts to Vcc switching. IC Acronym for Integrated Circuit. ICEM Acronym for Integrated Circuits Electromagic Model, specification 620203 from IEC. ICM Acronym for IBIS Interconnect Modeling Information (specification). Connectors, packages, and interconnections. idealgeneric models Examples: ideal current source, ideal operational amplifier. IEC 1. Acronym for International Engineering Consortium 2. Acronym for International Electrotechnical Commission IEEE Acronym for Institute of Electrical and Electronics Engineers. IGBT Acronym for Insulated Gate Bipolar Transistor. IGFET Acronym for Insulated Gate Field Effect Transistor. impedance Measured in ohms, it is the total opposition to the flow of current offered by a circuit element. Impedance consists of the vector sum of resistance and reactance. The symbol, or term, for impedance is Z. incontrol (SPC) A statistical process control (SPC) term that means that only random variation is seen in the process and that there are no special cause reasons for variation. IP Acronym for Intellectual Property. ISO Acronym for International Standards Organization. J JEDEC Acronym for Joint Electron Device Engineering Council. JFET Acronym for Junction Field Effect Transistor. junction Contact or connection between two or more wires or cables. The area where the ptype material and ntyp。