利用dsp实现自适应滤波dsp课程设计(编辑修改稿)

利用dsp实现自适应滤波dsp课程设计(编辑修改稿)内容摘要：

* BUFFSIZE, one ping and one pong buffer on both receive and transmit sides. */ pragma DATA_SECTION (gBufferXmtPing, buffer_sect)。 Int16 gBufferXmtPing[BUFFSIZE]。 // Transmit PING buffer pragma DATA_SECTION (gBufferXmtPong, buffer_sect)。 Int16 gBufferXmtPong[BUFFSIZE]。 // Transmit PONG buffer pragma DATA_SECTION (gBufferRcvPing, buffer_sect)。 Int16 gBufferRcvPing[BUFFSIZE]。 // Receive PING buffer pragma DATA_SECTION (gBufferRcvPong, buffer_sect)。 Int16 gBufferRcvPong[BUFFSIZE]。 // Receive PONG buffer pragma DATA_SECTION (delayone, .buffer_cahe)。 Int16 delayone[CAHE]。 // Receive PONG buffer pragma DATA_SECTION (delaytwo, .buffer_cahe)。 Int16 delaytwo[CAHE]。 // Receive PONG buffer /**/ // // Config McBSP: Use McBSP to send and receive the data between DSP and AIC23B // /**/ MCBSP_Config Mcbsp1Config = { MCBSP_SPCR1_RMK( MCBSP_SPCR1_DLB_OFF, // DLB = 0 MCBSP_SPCR1_RJUST_LZF, // RJUST = 0,right justify the data and zero fill 20 the MSBs MCBSP_SPCR1_CLKSTP_DISABLE, // CLKSTP = 0 MCBSP_SPCR1_DXENA_ON, // DXENA = 1,DX delay enabler on 0, // Reserved = 0 MCBSP_SPCR1_RINTM_RRDY, // RINTM = 0 MCBSP_SPCR1_RSYNCERR_NO, // RSYNCER = 0 // MCBSP_SPCR1_RFULL_NO, // RFULL = 0 // MCBSP_SPCR1_RRDY_NO, // RRDY = 0 MCBSP_SPCR1_RRST_DISABLE // RRST = 0。 Disable receiver ), MCBSP_SPCR2_RMK( MCBSP_SPCR2_FREE_NO, // FREE = 0 MCBSP_SPCR2_SOFT_NO, // SOFT = 0 MCBSP_SPCR2_FRST_FSG, // FRST = 1。 Enable the framesync logic MCBSP_SPCR2_GRST_CLKG, // GRST = 1。 The sample rate generator is take out of its reset state MCBSP_SPCR2_XINTM_XRDY, // XINTM = 0 MCBSP_SPCR2_XSYNCERR_NO, // XSYNCER =0 // MCBSP_SPCR2_XEMPTY_NO, // XEMPTY = 0 // MCBSP_SPCR2_XRDY_NO, // XRDY = 0 MCBSP_SPCR2_XRST_DISABLE // XRST = 0 Disable transimitter ), // 单数据相，接受数据长度为 16 位 ,每相 2 个数据 MCBSP_RCR1_RMK( MCBSP_RCR1_RFRLEN1_OF(1), // RFRLEN1 = 1 MCBSP_RCR1_RWDLEN1_16BIT // RWDLEN1 = 2 ), MCBSP_RCR2_RMK( MCBSP_RCR2_RPHASE_SINGLE, // RPHASE = 0 MCBSP_RCR2_RFRLEN2_OF(0), // RFRLEN2 = 0 MCBSP_RCR2_RWDLEN2_8BIT, // RWDLEN2 = 0 MCBSP_RCR2_RCOMPAND_MSB, // RCOMPAND = 0 No panding,any size data, MSB received first MCBSP_RCR2_RFIG_YES, // RFIG = 1 Framesync ignore MCBSP_RCR2_RDATDLY_1BIT // RDATDLY = 1 1bit data delay ), MCBSP_XCR1_RMK( MCBSP_XCR1_XFRLEN1_OF(1), // XFRLEN1 = 1 MCBSP_XCR1_XWDLEN1_16BIT // XWDLEN1 = 2 ), MCBSP_XCR2_RMK( MCBSP_XCR2_XPHASE_SINGLE, // XPHASE = 0 MCBSP_XCR2_XFRLEN2_OF(0), // XFRLEN2 = 0 MCBSP_XCR2_XWDLEN2_8BIT, // XWDLEN2 = 0 21 MCBSP_XCR2_XCOMPAND_MSB, // XCOMPAND = 0 MCBSP_XCR2_XFIG_YES, // XFIG = 1 Unexpected Framesync ignore MCBSP_XCR2_XDATDLY_1BIT // XDATDLY = 1 1bit data delay ), MCBSP_SRGR1_DEFAULT, MCBSP_SRGR2_DEFAULT, MCBSP_MCR1_DEFAULT, MCBSP_MCR2_DEFAULT, MCBSP_PCR_RMK( // MCBSP_PCR_IDLEEN_RESET, // IDLEEN = 0 MCBSP_PCR_XIOEN_SP, // XIOEN = 0 MCBSP_PCR_RIOEN_SP, // RIOEN = 0 MCBSP_PCR_FSXM_EXTERNAL, // FSXM = 0 Tranmit framesyn is provided by AIC23B MCBSP_PCR_FSRM_EXTERNAL, // FSRM = 0 Receive framesyn is provided by AIC23B MCBSP_PCR_CLKXM_INPUT, // CLKR is input MCBSP_PCR_CLKRM_INPUT, // CLKX is input MCBSP_PCR_SCLKME_NO, // SCLKME=0 CLKG is taken from the McBSP internal input clock // MCBSP_PCR_CLKSSTAT_0, // The signal on the CLKS pin is low MCBSP_PCR_DXSTAT_0, // Drive the signal on the DX pin low // MCBSP_PCR_DRSTAT_0, // The signal on the DR pin is low MCBSP_PCR_FSXP_ACTIVEHIGH, // FSXP = 1 Because a falling edge on LRCIN or LRCOUT starts data transfer MCBSP_PCR_FSRP_ACTIVELOW, // FSRP = 1 MCBSP_PCR_CLKXP_FALLING, // CLKXP = 1 The falling edge of BCLK starts data transfer MCBSP_PCR_CLKRP_RISING // CLKRP = 1 ), MCBSP_RCERA_DEFAULT, MCBSP_RCERB_DEFAULT, MCBSP_RCERC_DEFAULT, MCBSP_RCERD_DEFAULT, MCBSP_RCERE_DEFAULT, MCBSP_RCERF_DEFAULT, MCBSP_RCERG_DEFAULT, MCBSP_RCERH_DEFAULT, MCBSP_XCERA_DEFAULT, MCBSP_XCERB_DEFAULT, MCBSP_XCERC_DEFAULT, MCBSP_XCERD_DEFAULT, MCBSP_XCERE_DEFAULT, MCBSP_XCERF_DEFAULT, 22 MCBSP_XCERG_DEFAULT, MCBSP_XCERH_DEFAULT }。 DMA_Config dmaRcvConfig = { DMA_DMACSDP_RMK( DMA_DMACSDP_DSTBEN_NOBURST, DMA_DMACSDP_DSTPACK_OFF, DMA_DMACSDP_DST_DARAMPORT1, DMA_DMACSDP_SRCBEN_NOBURST, DMA_DMACSDP_SRCPACK_OFF, DMA_DMACSDP_SRC_PERIPH, DMA_DMACSDP_DATATYPE_16BIT ), /* DMACSDP */ DMA_DMACCR_RMK( DMA_DMACCR_DSTAMODE_POSTINC, DMA_DMACCR_SRCAMODE_CONST, DMA_DMACCR_ENDPROG_OFF, /* ENDPROG OFF */ DMA_DMACCR_WP_DEFAULT, DMA_DMACCR_REPEAT_OFF, DMA_DMACCR_AUTOINIT_ON, /* AUTOINIT ON */ DMA_DMACCR_EN_STOP, DMA_DMACCR_PRIO_LOW, DMA_DMACCR_FS_DISABLE, DMA_DMACCR_SYNC_REVT1 ), /* DMACCR */ DMA_DMACICR_RMK( DMA_DMACICR_AERRIE_ON, DMA_DMACICR_BLOCKIE_OFF,。