chargepumpsforpllsbyrfaddo(编辑修改稿)

chargepumpsforpllsbyrfaddo(编辑修改稿)内容摘要：

Type 5: High Voltage Charge Pumps  Design Considerations  Typical Charge Pump Designs  Charge Pump Design 1: Dual Compensation Charge Pump  Charge Pump Design 2: NMOS Topology for a Dual Compensation Charge Pump Implementation  Charge Pump Design 3: Dual Compension Implementation of a PMOS – NMOS Charge Pump Topology  Charge Pump Design 4: Low Voltage High Speed Charge Pump design  Charge Pump Design 5: Charge Pump Design for Ultra Low Power PLL  Charge Pump Design 6: Charge Pump Design for Low Phase Noise Low Power PLL  Charge Pump Design 7: A Fully Differential Charge Pump  Charge Pump Design 8: Charge Pump Design for a Low Power PLL  Summary  Reference  If the current values lup and Idn are not exactly same, or there is some delay between the controlled signals UP and DN, then there will be a natural phase error between reference frequency and output frequency of the VCO even if the PLL is in locked state.  The reason is that the voltage Vc must be constant when the PLL is locked. In other words the quantity of charge Qcharge and the one of discharge Qdischarge at the load CL must be equal at the time  Qcharge = lup x tup = Qdischarge = ldn x tdn  where tup and tdn are the charging and discharging times in one cycle  If the values of lup and Idn, are different, then there has to be a constant difference of switchon time Δt between SM1 and SM2 at every paring cycle, which means a relevant phase difference Δɵo exists at the two inputs of P/FD, as illustrated in Fig. 5.  Specifically, the phase difference Δɵo between reference frequency and the output frequency of the VCO will always exists, even when the whole loop is in a locked state. [5] Fig. 5. Mismatch issue in charge pump circuits.[5]  The classical method of reducing the current mismatch of the charge pump is to either increase the output resistance of the pump or to use a pensation method  The output resistance of the charge pump can be increased by either using a cascode or a gain – boosting topology. This will however reduce the output dynamic range and prevent the use of the pump for low voltage operations.  The pensation method is implemented by the use of operational amplifier.  The op – amp enables the pump currents to track each other and then pensate for any mismatch.  This will however result in higher power consumption and an area overhead due to the addition of the op – amp  Other sources of current mismatch are process variation and charge sharing [6]. CONVENTIONAL CHARGE PUMP  Fig 6a shows a conventional charge pump schematic and fig 6b shows the current matching characteristics  When the VCP is equal to the biasing voltage VR of the PMOS, the pump – up current IUP is equal to the pump – down current IDN  When the the VCP deviates from the VR, the difference between the pumping – up and the pumping – down current increases due to channel length modulation effect. [2] [2] Fig 6a. Schematic of conventional charge pump Fig 6b. Current matching characteristics the of conventional charge pump CASCODE METHOD  Fig 7a shows a schematic of a conventional cascode charge pump and fig 7b shows its current matching characteristics  In the cascode CP, more cascode devices must be stacked to increase the output resistance.  By increasing the output resistance, current mismatch can be reduced.  However, stacked cascode devices reduce the output dynamic range. COMPENSATION METHOD  This uses an op – amp to implement a negative feedback loop which controls the PMOS bias voltage VR so that it matches the output voltage VCP  This reduces the difference in current which causes the pump – up current and the pump – down current to be equal.  But there still exist a current variation with the VCP. [2], [3] Fig 7a. Schematic of conventional cascode charge pump [2] Fig 7b. Current matching characteristics the of conventional cascode CP [2] Fig 7c. Schematic of conventional pensated charge pump [2] Fig 7d. Current matching characteristics the of pensated CP [2]  Introduction  The Charge Pump  Basic Principle of Operation of a Conventional Charge Pump  Nonideal Behavior  Charge Sharing  Charge Injection and Clock Feedthrough  Current Mismatch  Charge pump architectures  Type 1: Conventional Tristate  Type 2: Current Steering Topology  Type 3: Differential Input with Single – Ended Output Topology  Type 4: Fully Differential Charge Pump Topology  Type 5: High Voltage Charge Pumps  Design Considerations  Typical Charge Pump Designs  Charge Pump Design 1: Dual Compensation Charge Pump  Charge Pump Design 2: NMOS Topology for a Dual Compensation Charge Pump Implementation  Charge Pump Design 3: Dual Compension Implementation of a PMOS – NMOS Charge Pump Topology  Charge Pump Design 4: Low Voltage High Speed Charge Pump design  Charge Pump Design 5: Charge Pump Design for Ultra Low Power PLL  Charge Pump Design 6: Charge Pump Design for Low Phase Noise Low Power PLL  Charge Pump Design 7: A Fully Differential Charge Pump  Charge Pump Design 8: Charge Pump Design for a Low Power PLL  Summary  Reference  This is also called the single – ended charge pump.  It has a lower current consumption depending on the frequency of the PFD  There are three topologies for this type of charge pump: the switch – in – drain, switch – in gate and switch – in – source. Switch – in – Drain  This charge pump has its switch at the drain of the current mirror device  When the switch DW is turned off, the c。