虚拟数字存储示波器毕业论文中英文资料外文翻译文献(编辑修改稿)

虚拟数字存储示波器毕业论文中英文资料外文翻译文献(编辑修改稿)内容摘要：

in theory if not need to show that the public can be a screen”. This was followed by the humanputer interface design. Ease of operation needs to be raised. In addition to the necessary selfbutton interface, the button should better. For example, switch interface automatically trigger procedures, and omit one of the switch button. In addition to the design of the interface graphics, there are too many forms, the ideal situation is designed to be hidden in control of the state model. Once again there is a regret. Can be designed as a dualchannel oscilloscope trace or more will be even more perfect. A highend oscilloscope usually have two channels, and some have more spectrum for the channel. In fact, the increase in access is not difficult, but also far more than the traditional highend oscilloscope the two channels. According to requirements of Title 32 of vertical resolution / div, oscilloscope, a total of eight grid, that is, divided into 256, the choice of eight A / D. Also because of the level of resolution of 20:00 / div, it corresponds to the third gear scan rate s / div, , 20us/div the sampling rate is respectively 100 HZ, 100KHZ and 1 MHZ. As follows: a scanning speed of Xs / div, the level of demand for the resolution of 20:00 / div, so every point of sampling interval for X/20s, that is, the sampling frequency signal for the 20 / X HZ. Therefore, when the scanning speed of third gear requirements for s / div, , 20us/div, corresponding to the third gear sampling frequency are 100 HZ, 100KHZ, 1MHZ. However, the 100 HZ to 100 KHZ the span too great, and not conducive to the middle band signals in the show, so we add a 1 KHZ and 10 KHZ Liangdang scanning speed. As the highest sampling rate to 1 MPS, so ordinary A / D to meet the requirements, so we selected TI39。 s eight COMS ADC TLC5510. The chip single5 V power supply, the conversion rate to a maximum 20 MPS, with a sampling of internal circuits and to maintain the benchmark resistance. The chip39。 s biggest advantage is fast, simple control, programmable device to control. A / D circuit as follows: The A / D circuit of the dynamic range of input signal for a small V ~ . In order to be extended to the dynamic range of 0 ~ 10 V, to be in its previous level by adding the following adjustment circuit. In addition to the circuit five times the input signal attenuation, the input signal is still on the superposition of the V DC. Control circuitry to do the programmable device, the main address cumulative unit, sampling speed option modules and programmable device and MCU interface unit. The address cumulative unit circuit as follows: CLK for the system clock, counting from the former firstchfa enter a negative pulse, D flipflop on the counter and reset, then the clock counting. When the full terms, the circuit automatically cease to work and produce a lowINT signal to mark the end of counting. Onf signal to latch signal, when it was low, latch the current sampling. The choice of memory chips and realtime considerations: Option 1: a sampling data storage RAM, to put the first postharvest methods of work. Circuit advantages of this method is simple, control simple, easy to implement. But only in the higher frequency when the input signal to a more stable output waveform, when the signal is very low, the output waveform update cycle is too long, the lack of realtime, and the output waveform data acquisition can not be carried out at the same time, some signal will be lost Information. Option 2: The two RAM, using a RAM storage of data collection, another film RAM output data, that is, two alternate RAM storage and output. The way to resolve some of the lost information signal, but the rate of mining must be consistent, otherwise the data will inevitably cause conflict. The method for lowfrequency signals no meaning, no good solution to the problem of realtime and more plex circuits, the occupation of mouth line resources, wastage. Programme 3: I use one pair of RAM, while mining release. The method simple circuit, the better solution of the problem so the realtime use of the programme. As the highest sampling rate is 1 MPS, it demands the greatest memory access time should be less than 1 us. As the level of demand for the resolution of 20:00 / div, and a total of 10 analog oscilloscope grid, that is, every time scanning should have 200 points, Therefore, storage of only 200 units. When the input signal an acquisition, the assumption that the largest full screen display a cycle of the signal, the storage period of 10 signals on the topic has been overmeet the requirements, the storage capacity as 2 K we choose the dualport RAM is IDT7132, the chip There are two symmetrical signal that each port has its own address lines, data lines and the Line of Control. The access time for the 25 ns ~ 35ns, storage capacity of 2 K, in the nonelected automatically in lowstatus, asynchronous operation, threestate input and output, and TTLlevel patible. Waveform display circuit: a waveform display XY manner and external trigger mode. However, in order to show the oscilloscope characters must choose XY approach. 1) Analysis of the data output rate: As the maximum speed of data acquisition for 1 MHZ, so data playback system scan rate should be more than 1 MHZ, can display realtime data update process. According to the experiment, we selected output frequency to 2 MHZ. In the output frequency, the realtime system better, and waveform stability, not distortion. We choose the DA is DAC0800, its output current setup time for the 100 ns, that is, 10 MHZ, the speed of data output to meet demand. Output data from the address by address accumulator, we address the accumulator after class to join the select level da。