光伏发电逆变器毕业论文中英文资料外文翻译文献(编辑修改稿)

光伏发电逆变器毕业论文中英文资料外文翻译文献(编辑修改稿)内容摘要：

y. The pare registers of the pare units are doublebuffered, allowing programmable change of the pare/PWM pulse widths as needed. Programmable deadband generator The deadband generator circuit includes three 8bit counters and an 8bit pare register. Desired deadband values (from 0 to 24 181。 s) can be programmed into the pare register for the outputs of the three pare units. The deadband generation can be enabled/disabled for each pare unit output individually. The deadbandgenerator circuit produces two outputs (with or 毕业论文 7 without deadband zone) for each pare unit output signal. The output states of the deadband generator are configurable and changeable as needed by way of the doublebuffered ACTR register. PWM waveform generation Up to eight PWM waveforms (outputs) can be generated simultaneously by each event manager: three independent pairs (six outputs) by the three fullpare units with programmable deadbands, and two independent PWMs by the GPtimer pares. PWM characteristics Characteristics of the PWMs are as follows:  16bit registers  Programmable deadband for the PWM output pairs, from 0 to 24 181。 s  Minimum deadband width of 50 ns  Change of the PWM carrier frequency for PWM frequency wobbling as needed  Change of the PWM pulse widths within and after each PWM period as needed  Externalmaskable power and driveprotection interrupts  Pulsepatterngenerator circuit, for programmable generation of asymmetric, symmetric, and fourspace vector PWM waveforms  Minimized CPU overhead using autoreload of the pare and period registers Capture unit The capture unit provides a logging function for different events or transitions. The values of the GP timer 2 counter are captured and stored in the twoleveldeep FIFO stacks when selected transitions are detected on capture input pins, CAPx (x = 1, 2, or 3 for EVA。 and x = 4, 5, or 6 for EVB). The capture unit consists of three capture circuits. Capture units include the following features:  One 16bit capture control register, CAPCON (R/W)  One 16bit capture FIFO status register, CAPFIFO (eight MSBs are readonly, eight LSBs are writeonly)  Selection of GP timer 2 as the time base  Three 16bit 2leveldeep FIFO stacks, one for each capture unit  Three Schmitttriggered capture input pins (CAP1, CAP2, and CAP3)—one input pin per capture unit. [All inputs are synchronized with the device (CPU) clock. In order for a transition to be captured, the input must hold at its current level to meet two rising edges of the device clock. The input pins CAP1 and CAP2 can also be used as QEP 毕业论文 8 inputs to the QEP circuit.]  Userspecified transition (rising edge, falling edge, or both edges) detection  Three maskable interrupt flags, one for each capture unit Enhanced analogtodigital converter (ADC) module A simplified functional block diagram of the ADC module is shown in Figure 1. The ADC module consists of a 10bit ADC with a builtin sampleandhold (S/H) circuit. Functions of the ADC module include:  10bit ADC core with builtin S/H  Fast conversion time (S/H + Conversion) of 500 ns  16channel, muxed inputs  Autosequencing capability provides up to 16 ―autoconversions‖ in a single session. Each conversion can be programmed to select any 1 of 16 input channels  Sequencer can be operated as two independent 8state sequencers or as one large 16state sequencer (., two cascaded 8state sequencers)  Sixteen re。