pld设计问答(编辑修改稿)

pld设计问答(编辑修改稿)内容摘要：

esults in a less reliable design. A mon technique to remove gated clock is to make use of the clock enable pin of the flipflop. For example, if you have a signal clko = clki amp。 a amp。 b driving the clock pin of a flipflop, you can eliminate the gated clock by feeding clki directly to the FF clock pin, and have another signal en = a amp。 b connected to the clock enable pin of the FF. ( 参考译文：在现代高速数字设计当中 , 不建议使用组合逻辑门控时钟信号 , 因为这将会在选通的时钟信号上产生短时脉冲波形干扰 , 导致错误触发 flipflop. 这是缺乏可靠性的设计 . 移除门控时钟通常所采用的技巧是使用 flipflop 的时钟使能引脚 . 例如 , 如果有一个信号 clko = clki amp。 a amp。 b 正在驱动 flipflop的时钟引脚 , 则可以通过直接将clki传递给 FF 时钟引脚 , 并将另一个信号 en = a amp。 b 与 FF的时钟使能引脚连接 , 来消除门控时钟 . ) By removing the gated clock, you no longer have the problem of clock delay. Also the design is more robust. (移除门控时钟后 , 就不再有时钟延迟的问题了 . 而且这种设计也比较可靠 . ) 30． FPGA生产产商提供了 IP, 如何用第三方软件 , 如 Advantage 或 ACTIVE vhdl, 调用并进行仿真。 答： The IPs provided by Xilinx, e. g. PCI, e with simulation models which can be processed by 3rd part simulation tools like Modelsim. So there is no problem for functional simulation. Timing simulation can be done by exporting the postlayout vhdl/verilog model from Xilinx ISE software. In some cases, sample testbenches are also included. （参考译文： Xilinx提供的 IP, 例如 PCI, 是与仿真模型一同提供的 , 这种模型可由第三方仿真工具 , 如Modelsim 来处理 . 因此对功能仿真来说 , 没有问题 . 通过从 Xilinx ISE 软件中导出postlayout vhdl/verilog可以执行定时仿真 . 在某些情况下 , 也包括样本测试平台 . ） 31． “ As a good design practice, never use gate delay to implement your delay logic under all circumstances” . Please tell me what does gate delay(闸 ) mean?（“一个好的设计 , 在所有情况下都决不会使用门延迟来实现延迟逻辑 . ”此处“门延迟”是什么意思。 ） 答： “ By gate delay I mean using a series of logic gates to introduce certain amount of delay in the design. This is highly undesirable since gate delay changes with factors like temperature and process technology. The design may fail as temperature changes or using a different version silicon. Also designs relying on gate delay are not portable, meaning that you need to redesign the whole circuit whenever you want to change to another product series or part number, simply because the gate delay changes as well. （参考译文：“门延迟”指得是使用一系列逻辑门将一定数量的延迟导入到设计中 . 既然门延迟更改像温度和处理技术这样的因素 , 所以 , 这是很不合适的 . 由于温度的改变或使用不同版本的芯片 , 设计可能会失败 . 依赖门延迟的设计也不是可移植的 , 也就是说 , 要更改另一产品系列或部件号时 , 需要重新设计整个电路 , 只因为更改了门延迟 . ） Always use fully synchronous design. You never need to reply on gate delay if your design is fully synchronous. （始终使用完全同步设计 . 如果设计是全同步的 , 则无需回应门延迟 . ） 32． This time I download another program to another chip SpartanII XC2S50PQ208 in another circuit, while it fails, and show the following message: . . . Checking boundaryscan chain integrity. . . ERROR:JTag Boundaryscan chain test failed at bit position 39。 339。 on instance 39。 ***39。 (a substitute for the real name of file). A problem may exist in the hardware configuration. Check that the cable, scan chain, and power connections are intact, that the specified scan chain configuration matches the actual hardware, and that the power supply is adequate and delivering the correct voltage. ERROR:JTag Boundary scan chain has been improperly specified. Please check your configuration and reenter the boundaryscan chain information. Boundaryscan chain validated unsuccessfully. ERROR:JTag : The boundaryscan chain has not been declared correctly. Verify the syntax and correctness of the device BSDL files, correct the files, reset the cable and retry this mand. With so many messages, I don39。 t know what to do! I try many times but only fail, and doubt whether there is something wrong with the circuit?But the powers checked in circuit are right. Would you please give me some advice to crack the problem?（有一次 , 将程序下载至 SpartanII XC2S50PQ208 芯片电路 , 结果发生了故障 , 并显示以下消息：“ . . . Checking boundaryscan chain integrity. . . ERROR:JTag Boundaryscan chain test failed at bit position 39。 339。 on instance 39。 ***39。 (实际的文件名 )” . 问题可能在硬件配置 . 检查了连线、扫描链路和电源接头都没有问题 . 特定的扫描链路配置与实际的硬件相 匹配 , 电源充足且 电压正常 . “ ERROR:JTag Boundary scan chain has been improperly specified. Please check your configuration and reenter the boundaryscan chain information. Boundaryscan chain validated unsuccessfully. ERROR:JTag : The boundaryscan chain has not been declared correctly. Verify the syntax and correctness of the device BSDL files, correct the files, reset the cable and retry this mand. ”这么多出错消息 , 什么原因 , 怎么办。 ） 答： Usually it is the result of a broken JTAG chain or noisy chain. Most monly, the cable is not connected properly, a trace is not correct on the board, other devices in the chain are causing a problem, or a noisy parallel port exists. Try using a different PC. You can also add a 4. 7K pullup on the PROG pin of the FPGA and see if it helps. （通常 , 这是由于中断的 JTAG链或噪声链 . 最常见的原因是 , 连线不正确 , 板子上的迹线不正确 , 链路中的其它器件导致问题 , 或者存在噪声并口 . 试一下使用不同的 PC. 也可以在 FPGA的 PROG引脚上增加一个4. 7K 的上拉电阻 , 看看是否有帮助 . ） 33． 在 VHDL 中 , 定义为 SIGNAL 的量起到什么作用。 什么时候需要定义这个量。 下面的程序 ARCHITECTURE EXER2_ARCH OF EXERCISE2 IS SIGNAL TEM: STD_LOGIC。 BEGIN TEM=PIN50 AND PIN51。 PIN8 =TEM。 END EXER2_ARCH。 和如下的程序有何区别。 ARCHITECTURE EXER2_ARCH OF EXERCISE2 IS BEGIN PIN8=PIN50 AND PIN51。 END EXER2_ARCH。 答： If PIN8 is declared in your port list, the 2 examples are identical. From a hardware design39。 s perspective, you can think of a vhdl signal as an electrical signal. So basically you can declare every object as signal. From a simulation39。 s perspective, there is a fundamental difference between signal and variable in vhdl. A variable is nothing more than an object that holds a value. A variable assignment occurs instantly in a vhdl simulation. Also, a variable can only exist within a process, so it cannot transfer values across processes. A signal, on the other hand, has a history of values. Whenever a signal。