microcontrollerarchitecture—pic18ffamily内容摘要:
ash) Data memory with addresses Also called Data Register or File Register FFF=212=16x256=4096=4K PIC18F452/4520 – Data Memory with Access Banks Three ways to access data registers: Direct using Bank Select Registers (BSR) Bank address (4bit) + Instruction (8bit) Indirect using File Select Registers (FSR) FSR contains the address of the data register Hence, MPU uses FSR Access Bank using General Purpose Registers (GPR) Data Memory Organization Data Memory up to 4k bytes Data register map with 12bit address bus 000FFF Divided into 256byte banks There are total of F banks Half of bank 0 and half of bank 15 form a virtual bank that is accessible no matter which bank is selected FFF=212=16x256=4096=4K Access RAM PIC16F8F2520/4520 Register File (data memory) Map 000h 07Fh 256 Bytes Bank 0 GPR Bank 1 GPR Bank 2 GPR Bank 13 GPR Bank 14 GPR Bank 15 GPR Access SFR Access RAM (GPR) Access SFR 080h 0FFh 100h 1FFh 200h 2FFh D00h DFFh E00h EFFh F00h FFFh F7Fh F80h 00h 7Fh 80h FFh Access Bank GPR=General Purpose Reg. SFR=Special Function Reg. PIC18F452 I/O Ports Five I/O ports PORT A through PORT E Most I/O pins are multiplexed Generally have eight I/O pins with a few exceptions Addresses already assigned to these ports in the design stage Each port is identified by its assigned Special Function Registers (SFR) – look at the previous slide PORTA (address of F80) PORTB (address of F81) these are part of data memory or register file TRISB must be set to specify signal direction of PORT B. Processes and Conditions of Data Transfer Interrupt is a process of munication between two devices If provides efficient munication between the two devices Examples: Sending a file to a printer, pressing a key on the key board External or Internal to the MPU Processes and Condi。microcontrollerarchitecture—pic18ffamily
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