chapter8cpuandmemorydesign,enhancement,and

chapter8cpuandmemorydesign,enhancement,and内容摘要：

verage instruction execution is approximately equal to the clock speed of the CPU  Problems from stalling  Instructions have different numbers of steps  Problems from branching 810 Copyright 2020 John Wiley amp。 Sons, Inc. Pipelining Example 811 Copyright 2020 John Wiley amp。 Sons, Inc. Branch Problem Solutions  Separate pipelines for both possibilities  Probabilistic approach  Requiring the following instruction to not be dependent on the branch  Instruction Reordering (superscalar processing) 812 Multiple, Parallel Execution Units  Different instructions have different numbers of steps in their cycle  Differences in each step  Each execution unit is optimized for one general type of instruction  Multiple execution units permit simultaneous execution of several instructions Copyright 2020 John Wiley amp。 Sons, Inc. 813 Copyright 2020 John Wiley amp。 Sons, Inc. Superscalar Processing  Process more than one instruction per clock cycle  Separate fetch and execute cycles as much as possible  Buffers for fetch and decode phases  Parallel execution units 814 Copyright 2020 John Wiley amp。 Sons, Inc. Superscalar CPU Block Diagram 815 Copyright 2020 John Wiley amp。 Sons, Inc. Scalar vs. Superscalar Processing 816 Copyright 2020 John Wiley amp。 Sons, Inc. Superscalar Issues  Outoforder processing – dependencies (hazards)  Data dependencies  Branch (flow) dependencies and speculative execution  Parallel speculative execution or branch prediction  Branch History Table  Register access conflicts  Rename or logical registers 817 Copyright 2020 John Wiley amp。 Sons, Inc. Memory Enhancements  Memory is slow pared to CPU processing speeds!  2Ghz CPU = 1 cycle in 189。