组合逻辑控制单元设计

组合逻辑控制单元设计内容摘要：

)。 end decoder38。 architecture behave of decoder38 is begin process(S) begin if S=39。 139。 then Y(0)=(not A(2)) and (not A(1)) and (not A(0))。 Y(1)=(not A(2)) and (not A(1)) and A(0)。 Y(2)=(not A(2)) and A(1) and (not A(0))。 Y(3)=(not A(2)) and A(1) and A(0)。 Y(4)=A(2) and (not A(1)) and (not A(0))。 Y(5)=A(2) and (not A(1)) and A(0)。 Y(6)=A(2) and A(1) and (not A(0))。 Y(7)=A(2) and A(1) and A(0)。 else Y=00000000。 end if。 end process。 end behave。 控制单元 38 译码器 i7 … i0 … Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 38 译码器 S A2 A1 A0 t0 q18 …… q0 m0 t1 控制单元 m1 t2 d7 … d0 m2 S A2 A1 A0 T0 T1 T2 M0 M1 M2 Q18 … Q0 library ieee。 use。 entity CU is port( m:in std_logic_vector(2 downto 0)。 t:in std_logic_vector(2 downto 0)。 d:in std_logic_vector(7 downto 0)。 q:out std_logic_vector(18 downto 0))。 end CU。 architecture behave of CU is signal iq:std_logic_vector(7 downto 0)。 begin iq(0)=not d(7) and not d(6) and not d(5) and not d(4) and not d(3) and not d(2) and not d(1) and d(0)。 iq(1)=not d(7) and not d(6) and not d(5) and not d(4) and not d(3) and not d(2) and d(1) and not d(0)。 iq(2)=not d(7) and not d(6) and not d(5) and not d(4) and not d(3) and d(2) and not d(1) and not d(0)。 iq(3)=not d(7) and not d(6) and not d(5) and not d(4) and d(3) and not d(2) and not d(1) and not d(0)。 iq(4)=not d(7) and not d(6) and not d(5) and d(4) and not d(3) and not d(2) and not d(1) and not d(0)。 iq(5)=not d(7) and not d(6) and d(5) and not d(4) and not d(3) and not d(2) and not d(1) and not d(0)。 iq(6)=not d(7) and d(6) and not d(5) and not d(4) and not d(3) and not d(2) and not d(1) and not d(0)。 iq(7)=d(7) and not d(6) and not d(5) and not d(4) and not d(3) and not d(2) and not d(1) and not d(0)。 q(0)=not m(2) and not m(1) and m(0) and not t(2) and not t(1) and t(0)。 q(1)=(not m(2) and not m(1) and m(0) and not t(2) and not t(1) and t(0)) or (not m(2) and m(1) and not m(0) and not t(2) and t(1) and not t(0) and iq(6))。 q(2)=not m(2) and not m(1) and m(0) and not t(2) and t(1) and not t(0)。