前瞻网路安全处理器及相关soc设计与测试技术研发

前瞻网路安全处理器及相关soc设计与测试技术研发内容摘要：

果進行電路設計及 硬體製作的研究 以全面同步局部非同步為主 的低功率系統架構之研發 混合同步非同步時序系統之 介面電路設計及系統架構之 合成工具 低功率之編譯器設計 可變電壓之排程 多階可程式輯輯陣列的架構設計 多階可程式輯輯陣列的分割工具 使用 Skill語言來完成自動佈局 產生器 針對可變電壓產生器的 電路硬體加以量測及驗證 , 並利用所得之數據評估此項 可變電壓技術的效能 分項計畫 B人力配置暨預算分配  子項計畫一：吳中浩教授 2博 2碩  子項計畫二：李政崑教授 2博 5碩 黃婷婷教授  子項計畫三：張世杰教授 2博 2碩  子項計畫四：黃柏鈞教授 2博 2碩  博士後研究 1 經費需求5 ,7 8 88 3 4 .51803 ,1 0 0人事費旅運費材料費業務費單位：仟元 Research Progress (Aug. 1, 2020) System Development Kits For SOC/IP Simulator Environment Retargetable Compilers and SDK Kits Hardware description language Fast System Software Prototyping An Example for Simulators and Development Kits for SOC/IP RF Baseband Link Manager Java Bluetooth API Applications SDP TCS HCI L2CAP Audio RFComm ArgumentsandLocalVariablesPr evio usCONST_POOLRe tu rn PCPr evio us VARSPr evio us FRAMECurr entMethod VectorFrameStatesOperandStackStack Frame ofMethod 0Stack Frame ofMethod 1::Stack CacheEntr y 0Entr y N 1VARSFRAMEN Entr ies32 bit s 32 bit s 32 bit sJava Processor IP Bluetooth IP Embedded SOC Design Methodology Trend?  rapidly exploring and evaluating different architectural and memory configurations  using a cycleaccurate simulator and retargetable optimizing piler to achieve the goal of meeting systemlevel performance, power, and cost objectives Shrinking timetomarket cycles Hardware Software design in parallel Architectural Description Language  ADL is a language designed to specify architecture templates for SOCs  Features that need to be considered: – Natural and concise specification – Generality in specification – Formal Model of specification – Automatic toolkit generation  ADL should capture all aspects of SOC design, including ASIC and I/O interfaces Benefits of ADL  Perform (formal) verification and consistency checking  Modify easily the target architecture and memory anization for design space exploration  Drive automatically the backend toolkit generation from a single specification  Adapt fast prototype of HDLbased high level synthesis by translation from ADL DSE: Design Space Exploration  The availability of a variety of processor cores, IP libraries (DSP, VLIW, SS/RISC, ASIP… ), and memory IP libraries (Cache, Buffer, SRAM, DRAM… ) presents a large exploration space for the choice of a base processor architecture. Optimizations with Specification in ADL  Timing model information ( instruction execution cycles, memory access cycles… ) directs piler optimizations in speed.  Power model information ( function unit and memory。