surveyofdigitalsignalprocessors

surveyofdigitalsignalprocessors内容摘要：

ALU SHIFTER B MAC A PC CNTL E C D ARs Specialized Instruction Sets  Base RISC ISA Plus CISC ISA Driven by End Application  MAC  SAD  LMS  FIRS  Viterbi  Support For Both Scalar and Vector Instructions  Support For 8, 16 and 32Bit Instructions  Instructions are Highly Orthogonal Scalar (55x) vs VLIW (64x)  Scalar DSP’s Tend to be More CISC Like  Hurts Compiler Performance  Improves EnergyDelay  Improves Code Density  Limits Top End Performance  VLIW DSP’s Tend to be More RISC Like  RISC + GP Regs + Orthogonality Makes For a Good C Compiler  Assembler Code Is Challenging  RISC ISA Allows for Higher Frequencies  LoadStore Hurts EnergyDelay TMS320C54x TMS320C54x Protected Pipeline CYCLES P1 D1 F2 P3 A1 D2 F3 P4 R1 A2 D3 F4 P5 X1 P6 R2 A3 D4 F5 F6 X2 R3 A4 D5 F1 P2 D6 X3 R4 A5 A6 X4 R5 R6 X5 X6 Fully loaded pipeline Note: Protected Pipeline Limits MicroArchitectural Flexibility and Performance Prefetch: Calculate address of instruction Fetch: Collect instruction Decode: Interpret instruction Access: Collect address of operand Read: Collect operand Execute: Perform operation TMS320C6xx Arithmetic Logic Unit Auxiliary Logic Unit Multiplier Unit ’C6xx CPU Core Data Path 1 D1 M1 S1 L1 A Register File Data Path 2 L2 S2 M2 D2 B Register File Instruction Decode Instruction Dispatch Program Fetch Interrupts Control Registers Control Logic Emulation Test TMS320C6xx Exposed Pipeline Fetch PG PS PW PR DP DC E1 E2 E3 E4 E5 Decode Execute Execute Packet 1  Fetch  PG Program Address Generate  PS Program Address Send  PW Program Access Ready Wait  PR Program。