introductiontocmosvlsidesignlogicaleffort

introductiontocmosvlsidesignlogicaleffort内容摘要：

Effort iGg o ut pa thin pa thCHCi i iF f g h10x y z20g 1 = 1h 1 = x / 1 0g 2 = 5 / 3h 2 = y / xg 3 = 4 / 3h 3 = z / yg 4 = 1h 4 = 2 0 / zCMOS VLSI Design Logical Effort Slide 21 Multistage Logic Networks  Logical effort generalizes to multistage works  Path Logical Effort  Path Electrical Effort  Path Effort  Can we write F = GH? iGg out pathin pathCHCi i iF f g hCMOS VLSI Design Logical Effort Slide 22 Paths that Branch  No! Consider paths that branch: G = H = GH = h1 = h2 = F = GH? 515159090CMOS VLSI Design Logical Effort Slide 23 Paths that Branch  No! Consider paths that branch: G = 1 H = 90 / 5 = 18 GH = 18 h1 = (15 +15) / 5 = 6 h2 = 90 / 15 = 6 F = g1g2h1h2 = 36 = 2GH 515159090CMOS VLSI Design Logical Effort Slide 24 Branching Effort  Introduce branching effort – Accounts for branching between stages in path  Now we pute the path effort – F = GBH o n pa th o f f pa tho n pa thCCbCiBb ih B HNote: CMOS VLSI Design Logical Effort Slide 25 Multistage Delays  Path Effort Delay  Path Parasitic Delay  Path Delay FiDf iPp iFD d D P  CMOS VLSI Design Logical Effort Slide 26 Designing Fast Circuits  Delay is smallest when each stage bears same effort  Thus minimum delay of N stage path is  This is a key result of logical effort – Find fastest possible delay – Doesn’t require calculating gate sizes iFD d D P  1ˆ Niif g h F1ND N F PCMOS VLSI Design Logical Effort Slide 27 Gate Sizes  How wide should the gates be for least delay?  Working backward, apply capacitance transformation to find input capacitance of each gate given load it drives.  Check work by verifying input cap spec is met. ˆˆoutiniiCCi outinf gh ggCCfCMOS VLSI Design Logical Effort Slide 28 Example: 3stage path  Select gate sizes x and y for least delay from A to B 8xxxyy4545ABCMOS VLSI Design Logical Effort Slide 29 Example: 3stage path Logical Effort G = Electrical Effort H = Branching Effort B = Path Effort F = Best Stage Effort Parasitic Delay P = Delay D = 8xxxyy4545ABˆf CMOS VLSI Design Logical Effort Slide 30 Example: 3stage path Logical Effort G = (4/3)*(5/3)*(5/3) = 100/27 Electrical Effort H = 45/8 Branching Effort B = 3 * 2 = 6 Path Effort F = GBH = 125 Best Stage Effort Parasitic Delay P = 2 + 3 + 2 = 7 Delay D = 3*5 + 7 = 22 = FO4 8xxxyy4545AB3ˆ 5fFCMOS VLSI Design Logical Effort Slide 31 Example: 3stage path  Work backward for sizes y = x = 8xxxyy4545ABCMOS VLSI Design Logical Effort Slide 32 Exampl。