removingtheidealmemoryassumptionthememory

removingtheidealmemoryassumptionthememory内容摘要：

y (SRAM) 1 2 Often used data + instructions EECC550 Shaaban 12 Lec 8 Winter 2020 212020 Access Locality amp。 Program Working Set • Programs usually access a relatively small portion of their address space (instructions/data) at any instant of time (program working set). • The presence of locality in program behavior and memory access patterns, makes it possible to satisfy a large percentage of program memory access needs using faster memory levels with much less capacity than program address space. Program Instruction Address Space Program instruction working set at time T0 Program instruction working set at time T0 + D Program Data Address Space Program data working set at time T0 Program data working set at time T0 + D Locality in program memory access Program Working Set Using Static RAM (SRAM) ( Cache) EECC550 Shaaban 13 Lec 8 Winter 2020 212020 Static RAM (SRAM) Organization Example 4 words X 3 bits each Static RAM (SRAM) Each bit can represented by a D flipflop Advantages over DRAM: Much Faster than DRAM No refresh needed (can function as onchip ideal memory or cache) Disadvantages: (reasons not used as main memory) Much lower density per SRAM chip than DRAM •DRAM one transistor per bit • SRAM 68 transistors per bit Higher cost than DRAM High power consumption D FlipFlip Thus SRAM is not suitable for main system memory but suitable for the faster/smaller cache levels EECC550 Shaaban 14 Lec 8 Winter 2020 212020 Levels of The Memory Hierarchy Part of The Onchip CPU Datapath ISA 16128 Registers One or more levels (Static RAM): Level 1: Onchip 1664K Level 2: Onchip 256K2M Level 3: On or Offchip 1M32M Registers Cache Level(s) Main Memory Magic Disc Optical Disk or Magic Tape Farther away from the CPU: Lower Cost/Bit Higher Capacity Increased Access Time/Latency Lower Throughput/ Bandwidth Dynamic RAM (DRAM) 256M16G Interface: SCSI, RAID, IDE, 1394 80G300G CPU Faster Access Time (Virtual Memory) Closer to CPU Core EECC550 Shaaban 15 Lec 8 Winter 2020 212020 A Typical Memory Hierarchy (With Two Levels of Cache) Control Datapath Virtual Memory, Secondary Storage (Disk) Processor Registers Main Memory (DRAM) Second Level Cache (SRAM) L2 1s 10,000,000s (10s ms) Speed (ns): 1s 10s 100s Gs Size (bytes): Ks Ms Tertiary Storage (Tape) 10,000,000,000s (10s sec) Ts Level One Cache L1 Larger Capacity Faster EECC550 Shaaban 16 Lec 8 Winter 2020 212020 Memory Hierarchy Operation • If an instruction or operand is required by the CPU, the levels of the memory hierarchy are searched for the item starting with the level closest to the CPU (Level 1 cache): – If the item is found, it’s delivered to the CPU resulting in a cache hit without searching lower levels. – If the item is missing from an upper level, resulting in a cache miss, the level just below is searched. – For systems with several levels of cache, the search continues with cache level 2, 3 etc. – If all levels of cache report a miss then main memory is accessed for the item. • CPU  cache  memory: Managed by hardware. – If the item is not found in main memory resulting in a page fault, then disk (virtual memory), is accessed for the item. • Memory  disk: Managed by the operating system with hardware support Hit rate for level one cache = H1 Miss rate for level one cache = 1 – Hit rate = 1 H1 Hit rate for level one cache = H1 Cache Miss L1 Cache EECC550 Shaaban 17 Lec 8 Winter 2020 212020 A block Memory Hierarchy: Terminology • A Block: The smallest unit of information transferred between two levels. • Hit: Item is found in some block in the upper level (example: Block X) – Hit Rate: The fraction of memory access found in the upper level. – Hit Time: Time to access the upper level which consists of RAM access time + Time to determine hit/miss • Miss: Item needs to be retrieved from a block in the lower level (Block Y) – Miss Rate = 1 (Hit Rate) – Miss Penalty: Time to replace a block in the upper level + Time to deliver the missed block to the processor • Hit Time Miss Penalty Lower Level Memory Upper Level Memory To Processor From Processor Blk X Blk Y cache main memory Miss rate for level one cache = 1 – Hit rate = 1 H1 Hit rate for level one cache = H1 e. g. H1 e. g. 1 H1 M (Fetch/Load) (Store) Ideally = 1 Cycle Ideally = 1 Cycle Typical Cache Block (or line) Size: 1664 bytes (S) M M Stall cycles on a miss Hit if block is found in cache Or Miss Time Miss EECC550 Shaaban 18 Lec 8 Winter 2020 212020 Basic Cache Concepts • Cache is the first level of the memory hierarchy once the address leaves the CPU and is searched first for the requested data. • If the data requested by the CPU is present in the cache, it is retrieved from cache and the data access is a cache hit otherwise a cache miss and data must be read from main memory. • On a cache miss a block of data must be brought in from main memory to cache to possibly replace an existing cache block. • The allowed block addresses where blocks can be mapped (placed) into cache from main memory is determined by cache placement strategy. • Locating a block of data in cache is handled by cache block identification mechanism (tag checking). • On a cache miss choosing the cache block being removed (replaced) is handled by the block replacement。