基于单片机ds18b20的数字温度计中英文献翻译

基于单片机ds18b20的数字温度计中英文献翻译内容摘要：

黄河科技学院毕业 论文 （文献翻译） 第 10 页 1Wire munication line by storing energy on an internal capacitor during periods of time when the signal line is high and continues to operate off this power source during the low times of the 1Wire line until it returns high to replenish the parasite (capacitor) supply. As an alternative, the DS18B20 may also be powered from an external 3 volt volt supply. DS18B20 BLOCK DIAGRAM Figure 1 Communication to the DS18B20 is via a 1Wire port. With the 1Wire port, the memory and control functions will not be available before the ROM function protocol has been established. The master must first provide one of five ROM function mands: 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Skip ROM, or 5) Alarm Search. These mands operate on the 64bit lasered ROM portion of each device and can single out a specific device if many are present on the 1Wire line as well as indicate to the bus master how many and what types of devices are present. After a ROM function sequence has been successfully executed, the memory and control functions are accessible and the master may then provide any one of the six memory and control function mands. One control function mand instructs the DS18B20 to perform a temperature measurement. The result of this measurement will be placed in the DS18B20’s scratchpad memory, and may be read by issuing a memory function mand which reads the contents of the scratchpad memory. The temperature alarm triggers TH and TL consist of 1 byte EEPROM each. If the alarm search mand is not applied to the DS18B20, these registers may be used as general purpose user memory. The scratchpad also contains a configuration byte to set the desired resolution of the temperature to digital conversion. Writing TH, TL, and 黄河科技学院毕业 论文 （文献翻译） 第 11 页 the configuration byte is done using a memory function mand. Read access to these registers is through the scratchpad. All data is read and written least significant bit first. 1WIRE BUS SYSTEM The 1Wire bus is a system which has a single bus master and one or more slaves. The DS18B20 behaves as a slave. The discussion of this bus system is broken down into three topics: hardware configuration, transaction sequence, and 1Wire signaling (signal types and timing). HARDWARE CONFIGURATION The 1Wire bus has only a single line by definition。 it is important that each device on the bus be able to drive it at the appropriate time. To facilitate this, each device attached to the 1Wire bus must have open drain or 3state outputs. The 1Wire port of the DS18B20 (DQ pin) is open drain with an internal circuit equivalent to that shown in Figure 9. A multidrop bus consists of a 1Wire bus with multiple slaves attached. The 1Wire bus requires a pullup The idle state for the 1Wire bus is high. If for any reason a transaction needs to be suspended, the bus MUST be left in the idle state if the transaction is to resume. Infinite recovery time can occur between bits so long as the 1Wire bus is in the inactive (high) state during the recovery period. If this does not occur and the bus is left low for more than 480 s, all ponents on the bus will be reset. HARDWARE CONFIGURATION TRANSACTION SEQUENCE 黄河科技学院毕业 论文 （文献翻译） 第 12 页。