基于at89c52单片机的交通灯控制系统的设计外文翻译8-bitmicrocontrollerwith8kbytesflashat89c52

基于at89c52单片机的交通灯控制系统的设计外文翻译8-bitmicrocontrollerwith8kbytesflashat89c52内容摘要：

ode. Interrupt Registers The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the six interrupt sources in the IP register. Data Memory The AT89C52 implements 256 bytes of onchip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. That means the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space. When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions that use direct addressing access SFR space. For example, the following direct addressing instruction accesses the SFR at location 0A0H . MOV 0A0H, data Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H). MOV @R0, data Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space. Timer 0 and 1 Timer 0 and Timer 1 in the AT89C52 operate the same way as Timer 0 and Timer 1 in the AT89C51. Timer 2 Timer 2 is a 16bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2 in the SFR 2 has three operating modes: capture, autoreload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON, as shown in Table 2 consists of two 8bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency. In the Counter function, the register is incremented in response to a 1to0 transition at its corresponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1to0 transition, the maximum count rate is 1/24 of the oscillator frequency. To ensure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle. Capture Mode In the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16bit timer or counter which upon overflow sets bit TF2 in bit can then be used to generate an interrupt. If EXEN2 = 1, Timer 2 performs the same operation, but a 1to0 transition at external input T2EX also causes the current value in TH2 and TL2 to be captured into RCAP2H and RCAP2L, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set. The EXF2 bit, like TF2 can generate an interrupt. The capture mode is illustrated in Figure 1. Autoreload (Up or Down Counter) Timer 2 can be programmed to count up or down when configured in i。