at89s52单片机毕业论文中英文文献翻译

at89s52单片机毕业论文中英文文献翻译内容摘要：

nes, Watchdog timer, two data pointers, three 16bit timer/counters, a sixvector twolevel interrupt architecture, a full duplex serial port, onchip oscillator, and clock circuitry. In addition, the AT89S52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Powerdown mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. Description VCC ： Supply voltage. GND ： Ground. Port 0： Port 0 is an 8bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as highimpedance inputs. Port 0 can also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode, P0 has internal pullups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pullups are required during program verification. Port 1： Port 1 is an 8bit bidirectional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups. In addition, and can be configured to be the timer/counter 2 external count input () and the timer/counter 2 trigger input (), respectively, as shown in the following table. Port 1 also receives the loworder address bytes during Flash programming and verification. Table1 Port Pin Alternate Functions T2 (external count input to Timer/Counter 2), clockout 无锡科技职业学院毕业论文中英文翻译 7 T2EX (Timer/Counter 2 capture/reload trigger and direction control) MOSI (used for InSystem Programming) MISO (used for InSystem Programming) SCK (used for InSystem Programming) Port 2： Port 2 is an 8bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 2 emits the highorder address byte during fetches from external program memory and during accesses to external data memory that use 16bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the highorder address bits and some control signals during Flash programming and verification. Port 3： Port 3 is an 8bit bidirectional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups. Port 3 receives some control signals for Flash programming and verification. Port 3 also serves the functions of various special features of the AT89S52, as shown in the following table. Table2 Port Pin Alternate Functions RXD (serial input port) TXD (serial output port) INT0 (external interrupt 0) 无锡科技职业学院毕业论文中英文翻译 8 INT1 (external interrupt 1) T0 (timer 0 external input) T1 (timer 1 external input) WR (external data memory write strobe) RD (external data memory read strobe) RST： Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives high for 98 oscillator periods after the Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO, the RESET HIGH out feature is enabled. ALE/ PROG ： Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input ( PROG ) during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALEdisable bit has no effect if the microcontroller is in external execution mode. PSEN ： Program Store Enable ( PSEN ) is the read strobe to external program memory. When the AT89S52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. EA /VPP： External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12volt programming enable voltage (VPP) during Flash programming. XTAL1： Input to the inverting oscillator amplifier and input to the internal clock operating c。