at89c51单片机外文资料

at89c51单片机外文资料内容摘要：

e reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. Program Memory Lock Bits On the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below. When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly. 沈阳航空工业学院电子工程系毕业设计（ 外文翻译 ） 12 Synthesis of an 8051Like MicroController Tolerant to Transient Faults This paper presents the implementation of a fault detection and correction technique used to design a robust 8051 microcontroller with respect to a particular transient fault called Single Event Upset (SEU). A specific study regarding the effects of a SEU in the microcontroller behavior was performed. Furthermore, a fault tolerant technique was implemented in a version of the 8051. The VHDL description of the faulttolerant microprocessor was prototyped in a FPGA environment and results in terms of area overhead, level of protection and performance penalties are discussed. 1. Introduction The constant improvements achieved in the microelectronics technology allow the manufacturing of very plex circuits, substituting boards or even puters of the past 80’s. Nowadays, because of the microelectronics advances, traditional applications bee cheaper and more reliable, while a large range of new applications can take advantage of integrated devices by using the socalled embedded systems. In all cases, architectures are strongly based on some kind of data processor, such as a microcontroller or a DSP processing unit, for example. The continuous decrease in the semiconductor dimensions and in electrical features, leads to an increasing sensitivity to some effects of the environment (ionization due to radiation, magic perturbations, thermal,...) considered minor or negligible in the technologies of the past. Particularly, digital circuits operating in space are subject to different kinds of radiation. However, some problems have also been reported for some Earth applications, like avionics systems . Radiation effects can be permanent or transient . Permanent faults result from particles trapped at the silicon/oxide interfaces and appear only after long exposure to radiation (Total Ionization Dose). Transient faults (Single Event Effects, SEE) may be caused by the impact of a single charged particle in sensitive zones of the circuit. Depending on the impact location, two kind of SEEs are distinguished: SELs (Single Event Latchups) and SEUs (Single Event Upsets). SELs result from the triggering of 沈阳航空工业学院电子工程系毕业设计（ 外文翻译 ） 13 parasitic thyristors (present in CMOS technologies) and provoke short circuits, capable to damage the ponent by thermal effect if the circuit is not poweredoff at time. SEUs are responsible for transient changes, called upsets or bit flips, in bits of information stored within an integrated circuit. Total ionization dose (TID) and single event latchup (SEL) effects can be reduced to acceptable levels using some of the existing CMOS technologies, for example the Epibulk CMOS process . However, Single Event Upsets (SEUs) represent radiation induced hazards, which are more difficult to avoid in the space applications, especially in highdensity submicron integrated circuits. In this paper, only SEU faults are being considered. The consequences of a SEU fault depend on the nature of the perturbed information, ranging from erroneous results to system crashes. For plex circuits like DSP processors, coprocessors, microcontrollers, the sensitivity to SEU correlates strongly with the amount of internal memory (registers, memory bits, flipflops, etc.) available. In this context, it is clear the need for circuits immune to radiation effects, mainly those working in space, where a fault can imply the lost of millions of dollars and years of work. Moreover, it is extremely important to know the efficiency of a faulttolerant technique before the circuit is in its real environment. This paper aims at investigating the efficiency of a fast prototyping design hardening technique, which focuses on generalpurpose processor architectures. The proposed technique is mainly based on the inclusion of error detecting and correcting capabilities. A reduced instruction set version of a wellknown microcontroller, the 8051 from Intel, was chosen as the test vehicle for these researches. This choice was motivated by the fact that this microcontroller is widely used in space applications. The paper is anized as follows: in Section 2 some related works are revisited. In Section 3 the effects of transient faults in a microcontroller are presented along with a tool capable to emulate the real process of a SEU fault occurrence. The implementation of a hardened 8051 microcontroller is presented in Section 4. Experimental results, concerning both the performance in terms of area overhead and operating frequency, and the sensitivity to transient bit flips, are summarized in Section 5. Section 6 brings some considerations about the implementation of a prototype of the faulttolerant circuit to be tested in a real radiation environment. Concluding remarks and future work are discussed in Section 7. 2. Related Work 沈阳航空工业学院电子工程系毕业设计（ 外文翻译 ） 14 Solutions to implement a fault tolerant device with respect to transient faults can be considered at different steps of the device de。