基于vhdl语言的8位risc-cpu的设计文献翻译

基于vhdl语言的8位risc-cpu的设计文献翻译内容摘要：

d_data_1 = read_data_1, Read_data_2 = read_data_2, Sign_extend = Sign_extend, Function_opcode = Instruction( 5 DOWNTO 0 ), ALUOp = ALUop, ALUSrc = ALUSrc, Zero = Zero, ALU_Result = ALU_Result, Add_Result = Add_Result, PC_plus_4 = PC_plus_4, 外文翻译（原文） 10 Clock = clock, Reset = reset )。 MEM dmemory PORT MAP ( read_data = read_data, address = ALU_Result, write_data = read_data_2, MemRead = MemRead, Memwrite = MemWrite, clock = clock, reset = reset )。 END structure。 The Control Unit The control unit of the MIPS shown in Figure examines the instruction opcode bits and generates eight control signals used by the other stages of the processor. Recall that the high six bits of a MIPS instruction contain the opcode. The opcode value is used to determine the instruction type. Figure Block Diagram of MIPS Control Unit control module (implements MIPS control unit) LIBRARY IEEE。 USE。 USE。 USE。 ENTITY control IS PORT( Opcode IN STD_LOGIC_VECTOR( 5 DOWNTO 0 )。 RegDst OUT STD_LOGIC。 ALUSrc OUT STD_LOGIC。 MemtoReg OUT STD_LOGIC。 RegWrite OUT STD_LOGIC。 MemRead OUT STD_LOGIC。 MemWrite OUT STD_LOGIC。 Branch OUT STD_LOGIC。 ALUop OUT STD_LOGIC_VECTOR( 1 DOWNTO 0 )。 clock, reset IN STD_LOGIC )。 END control。 外文翻译（原文） 11 ARCHITECTURE behavior OF control IS SIGNAL R_format, Lw, Sw, Beq STD_LOGIC。 BEGIN Code to generate control signals using opcode bits R_format = 39。 139。 WHEN Opcode = 000000 ELSE 39。 039。 Lw = 39。 139。 WHEN Opcode = 100011 ELSE 39。 039。 Sw = 39。 139。 WHEN Opcode = 101011 ELSE 39。 039。 Beq = 39。 139。 WHEN Opcode = 000100 ELSE 39。 039。 RegDst = R_format。 ALUSrc = Lw OR Sw。 MemtoReg = Lw。 RegWrite = R_format OR Lw。 MemRead = Lw。 MemWrite = Sw。 Branch = Beq。 ALUOp( 1 ) = R_format。 ALUOp( 0 ) = Beq。 END behavior。 The Instruction Fetch Stage The instruction fetch stage of the MIPS shown in Figure contains the instruction memory, the program counter, and the hardware to increment the program counter to pute the next instruction address. Figure Block Diagram of MIPS Fetch Unit 外文翻译（原文） 12 Instruction memory is implemented using the Altsyncram megafunction. 256 by 32 bits of instruction memory is available. This requires two of the Cyclone chip‘s M4K RAM memory blocks. Since the Altsyncram memory requires an address register, the PC register is actually implemented inside the memory block. A copy of the PC external to the memory block is also saved for use in simulation displays. Ifetch module (provides the PC and instruction memory for the MIPS puter) LIBRARY IEEE。 USE。 USE。 USE。 LIBRARY altera_mf。 USE。 ENTITY Ifetch IS PORT( SIGNAL Instruction OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 )。 SIGNAL PC_plus_4_out OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 )。 SIGNAL Add_result IN STD_LOGIC_VECTOR( 7 DOWNTO 0 )。 SIGNAL Branch IN STD_LOGIC。 SIGNAL Zero IN STD_LOGIC。 SIGNAL PC_out OUT STD_LOGIC_VECTOR( 9 DOWNTO 0 )。 SIGNAL clock, reset IN STD_LOGIC)。 END Ifetch。 ARCHITECTURE behavior OF Ifetch IS SIGNAL PC, PC_plus_4 STD_LOGIC_VECTOR( 9 DOWNTO 0 )。 SIGNAL next_PC STD_LOGIC_VECTOR( 7 DOWNTO 0 )。 BEGIN ROM for Instruction Memory data_memory altsyncram GENERIC MAP ( operation_mode = ROM, width_a = 32, widthad_a = 8, lpm_type = altsyncram, outdata_reg_a = UNREGISTERED, Reads in mif file for initial data memory values init_file = , intended_device_family = Cyclone) Fetch next instruction from memory using PC PORT MAP ( 外文翻译（原文） 13 clock0 = clock, address_a = Mem_Addr, q_a = Instruction)。 Instructions always start on a word address not byte PC(1 DOWNTO 0) = 00。 copy output signals allows read inside module PC_out = PC。 PC_plus_4_out = PC_plus_4。 send word address to inst. memory address register Mem_Addr = Next_PC。 Adder to increment PC by 4 PC_plus_4( 9 DOWNTO 2 ) = PC( 9 DOWNTO 2 ) + 1。 PC_plus_4( 1 DOWNTO 0 ) = 00。 Mux to select Branch Address or PC + 4 Next_PC = X‖00‖ WHEN Reset = ‗1‘ ELSE Add_result WHEN ( ( Branch = 39。 139。 ) AND ( Zero = 39。 139。 ) ) ELSE PC_plus_4( 9 DOWNTO 2 )。 Store PC in register and load next PC on clock edge PROCESS BEGIN WAIT UNTIL ( clock39。 EVENT ) AND ( clock = 39。 139。 )。 IF reset = 39。 139。 THEN PC = 0000000000。 ELSE PC( 9 DOWNTO 2 ) = Next_PC。 END IF。 END PROCESS。 END behavior。 The MIPS program is contained in instruction memory. Instruction memory is automatically initialized using the file shown in Figure . This initialization only occurs once during download and not at a reset. For different test programs, the appropriate machine code must be entered in this file in hex. Note that the memory addresses displayed in the file are word addresses while addresses in registers such as the PC are byte addresses. The byte address is four times the word address since a 32bit word contains four bytes. Only word addresses can be used in the *.mif files. 外文翻译（原文） 14 Figure MIPS Program Memory Initialization File, The Decode Stage The decode stage of the MIPS contains the register file as shown in Figure . The MIPS contains thirtytwo 32bit registers. The register file requires a major portion of the hardware required to implement the MIPS. Registers are initialized to the register number during a reset. This is done to enable the use of shorter test programs that do not have to load all of the registers. A VHDL FOR...LOOP structure is used to generate the initial register values at reset. 外文翻译（原文） 15 Figure Block Diagram of MIPS Decode Unit Idecode module (implements the register file for the MIPS puter) LIBRARY IEEE。 USE。 USE。 USE。 ENTITY Idecode IS PORT( read_data_1 OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 )。 read_data_2 OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 )。