at89c51外文翻译毕业设计

at89c51外文翻译毕业设计内容摘要：

is powered up without a reset the latch initializes to a random value and holds that value until reset is activated It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly Programming the Flash The AT89C51 is normally shipped with the onchip Flash memory array in the erased state that is contents FFH and ready to be programmed The programming interface accepts either a highvoltage 12volt or a lowvoltage VCC program enable signal The lowvoltage programming mode provides a convenient way to program the AT89C51 inside the users system while the highvoltage programming mode is patible with conventional thirdparty Flash or EPROM programmersThe AT89C51 is shipped with either the highvoltage or lowvoltage programming mode enabled The respective topside marking and device signature codes are listed in the following table The AT89C51 code memory array is programmed bytebybyte in either programming mode To program any nonblank byte in the onchip Flash Memory the entire memory must be erased using the Chip Erase Mode Programming Algorithm Before programming the AT89C51 the address data and control signals should be set up according to the Flash programming mode table and Figures 3 and 4 To program the AT89C51 take the following steps 1 Input the desired memory location on the address lines 2 Input the appropriate data byte on the data lines 3 Activate the correct bination of control signals 4 Raise EAVPP to 12V for the highvoltage programming mode 5 Pulse ALEPROG once to program a byte in the Flash array or the lock bits The bytewrite cycle is selftimedand typically takes no more than 15 ms Repeat steps 1 through 5 changing the address and data for the entire array or until the end of the object file is reached Data Polling The AT89C51 features Data Polling to indicate the end of a write cycle During a write cycle an attempted read of the last byte written will result in the plement of the written datum on PO7 Once the write cycle has been pleted true data are valid on all outputs and the next cycle may begin Data Polling may begin any time after a write cycle has been initiated ReadyBusy The progress of byte programming can also be monitored by the RDYBSY output signal P34 is pulled low after ALE goes high during programming to indicate BUSY P34 is pulled high again when programming is done to indicate READY Program Verify If lock bits LB1 and LB2 have not been programmed the programmed code data can be read back via the address and data lines for verification The lock bits cannot be verified directly Verification of the lock bits is achieved by observing that their features are enabled Chip Erase The entire Flash array is erased electrically by using the proper bination of control signals and by holding ALEPROG low for 10 ms The code array is written with all 1s The chip erase operation must be executed before the code memory can be reprogrammed Reading the Signature Bytes The signature bytes are read by the same procedure as a normal verification of locations 030H 031H and 032H except that P36 and P37 must be pulled to a logic low The values returned are as follows 030H 1EH indicates manufactured by Atmel 031H 51H indicates 89C51 032H FFH indicates 12V programming 032H 05H indicates 5V programming Programming Interface Every code byte in the Flash array can be written and the entire array can be erased by using the appropriate bination of control signals The write operation cycle is selftimed and once initiated will automatically time itself to pletion All major programming vendors offer worldwide support for the Atmel microcontroller series Please contact your local programming vendor for the appropriate software revision Flash Programming and Verification Waveforms Highvoltage Mode VPP 12V Flash Programming and Verification Waveforms Lowvoltage Mode VPP 5V Flash Programming and Verification Characteristics TA 0176。 C to 70176。 C VCC 50 177。 10 Absolute imum Ratings NOTICE Stresses b。