外文翻译基于单片机的频率计设计

外文翻译基于单片机的频率计设计内容摘要：

R(15:14)=11 are branches. Aside form the S field and the SHA field for shifts, the format is the same as for IR(15:14)=01. For all instructions of this type, the destination address (not the operand) bees the new address placed in the program counter PC. As a consequence, the register mode is invalid for branch instructions. Before proceeding to the next step, which defines the datapath to support the instruction set architecture, we will briefly note the characteristics of the architecture that define it as CISC or RISC. Most of the operations given in Chapter 9 are included in the instruction set. A number of operations that do not appear are redundant. The same actions can be achieved by using proper addressing modes with instructions that do appear. For example, LD, ST, IN, and OUT can all be achieved by using MOVE instructions in a memorymapped structure. By looking at the formats for the instructions, we find that most of the instructions can operate directly on operate directly on operands from memory. There are eight addressing modes and two different lengths of instruction formats. In addition, some of the instructions perform plex operations which can be viewed as operations that are likely to take more than one clock cycle for the execution step. These characteristics clearly identify this as a CISC architecture. 4 Datapath anization Rather than beginning from scratch, we will reuse the nonpipelined datapath employed with the microprogrammed control in section 810, with modifications. That datapath was shown in section 810, and the new, modified datapath based on it is given in Figure 106. we treat each modification in turn, beginning with the register file. In section 810, register R8 was used as a temporary storage location. In the new microprogrammed architecture, there are plex instructions spanning many clock cycles and performing plicated operations. Thus, more temporary storage is needed for use by the microprograms. To meet this need, we expand the register file from 9 registers to 16. the first 8 registers, R0 through R7, are visible to the puter programmer. The second 8 registers, R8 though R15 , are used as temporary storage for the microprogram operands and are hidden from the programmer. Figure 103 provides a map of the expanded register file with the temporary registers shaded. As indicated previously, register R0 supplies the constant 0. registers R1 through R7 are available to the programmer for use, and registers R8 through R15 provide general temporary storage for use by microprograms, the last four registers, R12 though R15, have special uses: to keep the microcode simple, standard locations are essential for storing the operands and addresses used by execution microcode for most instructions. thus ,R12 is the location for the source address(SA), R13 for the source data (SD), R14 for the destination address(DA), and R15 for the destination data(DD). We cannot access the eight temporary registers based on the 3bit register address available in the instruction. To deal with this problem, we provide, first, 4bit register address from the microinstruction, and second, a microinstruction bit to choose between these addresses and those from the instruction. In addition, the flexibility to allow the register addressed by DST to be a source and by SRC to be a destination is needed to permit results of 5 operations to be placed directly in memory. To acplish these goals, we modify the register file by adding the logic shown in Figure 104(a). the instruction set architecture uses two addresses, one for a source a operand and the other for the other source as well as the destination. The register file uses the B address for a source, and the A and D addresses on the file are connected together, giving the same address for the other source and the destination. Although this reduction from three to two addresses is not essential at the mincroinstruction level, it decrease the number of bits needed for register addresses in the microinstruction and matches the use of the register fields in the instruction formats. A quad 2to1 multiplexer is attached。