单片机设计--毕业设计外文翻译

单片机设计--毕业设计外文翻译内容摘要：

real circuit clock tree can not achieve the ideal assumption that the clock, so we must be based on an ideal clock, the clock real work to build a model to analyze the circuit, so as to make the circuit performance and the practical work as expected . Clock in the actual model, we have to consider the spread of clocktree skew, vertical jump and absolute bias and other uncertainties. To register, the clock was working along the arrival of the data terminal when it should have been stable, so as to ensure that the work along the sampling clock to the accuracy of the data, this data preparation time that we call setup time (setup time). Data should also be working along the clock to maintain over a period of time, this period of time known as the hold time (hold time). Global clock for a design project, the global clock (or clock synchronous) is the simplest and most predictable clock. In the PLD / FPGA design of the clock the best options are: by a dedicated global clock input pins of a single master clockdriven clock design projects to each flipflop. As long as possible should be used in the design of global clock projects. PLD / FPGA has a dedicated global clock pins, the device is directly connected to each register. 毕业设计（论文） 4 Global clock to provide such a device in the shortest possible delay to the output clock. Clockgated in many applications, the entire design of the overall use of external clock is not possible or practical. With the product of PLD logic array clock (that is, the clock is generated by the logic), to allow arbitrary function alone all trigger clock. However, when you use the array clock, the clock should be carefully analyzed the function, in order to avoid glitches. Usually constitute the array clock clockgated. Clock gating often interface with the microprocessor, and used the address to write to control the pulse line. However, when using bination of flipflop when the clock function, usually there is a clockgated. If the following conditions, such as clock gating can be as reliable as global clock work: Drive the clock logic must contain only one and the door or a or gate. If any additional work in some state of logic, the petition will be the burr. A logic gate input as the actual clock, and the logic gate must be of all other input as the address or control lines, in relation to their pliance with the establishment and maintenance of clock time bound. Multilevel logic generated clock when the clockgating logic of the bination of more than one (or more than the individual and doors or or gate), the e。