单片机外文翻译---使用8051单片机验证和测试单粒子效应的加固工艺-单片机(编辑修改稿)

单片机外文翻译---使用8051单片机验证和测试单粒子效应的加固工艺-单片机(编辑修改稿)内容摘要：

to reset program counter if it wanders out of code space. • An external telemetry data storage memory to provide backup of data in the event of an interruption in data transmission. The brief description of each of the software tests used is given below. It should be noted that for each test, the returned telemetry （ including time tag） was sent to both the test controller and the telemetry memory, giving the highest reliability that all data is captured. Interrupt – This test used 4 of 6 available interrupt vectors （ Serial, External, Timer0 Overflow, and Timer1 Overflow） to trigger routines that sequentially modified a value in the accumulator which was periodically pared to a known value. Unexpected values were transmitted with register information. Logic – This test performed a series of logic and math putations and provided three types of error identifications: 1） addition/subtraction, 2） logic and 3） multiplication/division. All misputes of putations and expected results were transmitted with other relevant register information. Memory – This test loaded internal data memory at locations D:0x20 through D:0xff （ or D:0x20 through D:0x080 for the Culprit DUT） , indirectly, with an 0x55 pattern. Compares were performed continuously and misputes were corrected while error information and register values were transmitted. Program Counter The program counter was used to continuously fetch constants at various offsets in the code. Constants were pared with known values and misputes were transmitted along with relevant register information. Registers – This test loaded each of four （ 0,1,2,3） banks of generalpurpose registers with either 0xAA （ for banks 0 and 2） or 0x55 （ for banks 1 and 3） . The pattern was alternated in order to test the Program Status Word （ PSW） special function register, which controls generalpurpose register bank selection. Generalpurpose register banks were then pared with their expected values. All misputes were corrected and error information was transmitted. Special Function Registers （ SFR） – This test used learned static values of 12 out 21 available SFRs and then constantly pared the learned value with the current one. Misputes were reloaded with learned value and error information was transmitted. Stack – This test performed arithmetic by pushing and popping operands on the stack. Unexpected results were attributed to errors on the stack or to the stack pointer itself and were transmitted with relevant register information. VII. TEST METHODOLOGY The DUT Computer booted by executing the instruction code located at address 0x0000. Initially, the device at this location was an EPROM previously loaded with Boot/Serial Loader code. This code initialized the DUT Computer and interface through a serial connection to the controlling puter, the Test Controller. The DUT Computer downloaded Test Code and put it into Program Code RAM （ located on the Main Board of the DUT Computer） . It then activated a circuit which simultaneously performed two functions: held the DUT reset line active for some time （ ~10 ms）。 and, remapped the Test Code residing in the Program Code RAM to locate it to address 0x0000 （ the EPROM will no longer be accessible in the DUT Computer39。 s memory space） . Upon awaking from the reset, the DUT puter again booted by executing the instruction code at address 0x0000, except this time that code was not be the Boot/Serial Loader code but the Test Code. The Test Control Computer always retained the ability to force the reset/remap function, regardless of the DUT Computer39。 s functionality. Thus, if the test ran without a Single Event Functional Interrupt （ SEFI） either the DUT Computer itself or the Test Controller could have terminated the test and allowed the posttest functions to be executed. If a SEFI occurred, the Test Controller forced a reboot into Boot/Serial Loader code and then executed the posttest functions. During any test of the DUT, the DUT exercised a portion of its functionality （ ., Register operations or Internal RAM check, or Timer operations） at the highest utilization possible, while making a minimal periodic report to the Test Control Computer to convey that the DUT Computer was still functional. If this report ceased, the Test Controller knew that a SEFI had occurred. This periodic data was called telemetry. If the DUT encountered an error that was not interrupting the functionality （ ., a data register mispute） it sent a more lengthy report through the serial port describing that error, and continued with the test. VIII. DISCUSSION A. Single Event Latch up The main argument for why latch up is not an issue for the Culprit devices is that the operating voltage of volts should be below the holding voltage required for latch up to occur. In addition to this, the cell library used also incorporates the heavy dual guardbarring scheme [4]. This scheme has been demonstrated multiple times to be very effective in rendering CMOS circuits pletely immune to SEL up to test limits of 120 MeVcm2/mg. This is true in circuits operating at 5, , and Volts, as well as the Volt Culprit circuits. In one case, a 5 Volt circuit fabricated on noncircuits wafers even exhibited such SEL immunity. B. Single Event Upset The primary structure of the storage unit used in the Culprit devices is the Single Event Resistant Topology （ SERT） [5]. Given the SERT cell topology and a single upset node assumption, it is expected that the SERT cell will be pletely immune to SEUs occurring internal to the memory cell itself. Obviously there are other things going on. The。