计算机专业毕业论文外文翻译--输入输出访问(编辑修改稿)

计算机专业毕业论文外文翻译--输入输出访问(编辑修改稿)内容摘要：

ces and handle their interrupt requests by some policy, typically by priority. Only one request with the highest priority can be serviced at the current time, while all others are put into a waiting queue. Upon the pletion of the service performed by an interrupt service routine, the processor should search the waiting queue for all the pending interrupt requests, old or new, and continue to service them one by one according to their priorities, until the queue bees empty. Only when all the pending interrupt requests have been serviced can the interrupted user program be resumed. Although this case contains multiple interrupt requests, it is still a simplified case. The assumption is that all the interrupt service routines must be pleted without further interruption 9 (or socalled preemption) once they have been started one after another by the processor. An interrupt process satisfying this assumption is called a nonpreemptive interrupt. In reallife circumstances, the process of interruptdriven I/O can be more plicated than this simplified case. Each interrupted service routine running in the processor can be preempted (interrupted) by a newly arrived interrupt request, which has a higher priority than the current one. This circumstance will cause the main program and all the requested interrupt service routines to have a plicated interrelationship. An interrupt process that allows an interrupt service routine to be preempted by a higherpriority interrupt service routine is called a preemptive interrupt. Direct Memory Access Although interrupt I/O is more efficient than the programmed I/O, it still suffers from a relatively high overhead with respect to handling the interrupt. This overhead includes resolving the conflict among multiple interrupt requests, saving and restoring the program contexts, pooling for interrupt identification, branching to/from the interrupt service routine, etc. Using an interrupt is a wasteful activity that can take several microseconds to plete. Direct memory access (DMA) is a method that can input/output a block of data directly to/form main memory with a speed of one data item per memory cycle, without continuous involvement of the processor. The entire process is implemented by the hardware of a DMA controller, which takes the place of the processor and municates directly with main memory. As a result, the block diagram of the puter system changes form processorcentered to memorycentered. Hence, from the viewpoint of I/O processing, the processor is no longer the center of a puter, but rather a partner with which the I/O subsystem petes for memory bus cycles to input/output data item to/from main memory. However, a DMA controller is designed to exchange data in blocks, so it works well with the largevolume highspeed blockoriented I/O devices, such as highspeed disks and munication works. The DMA controller can work in two different modes. Normally, it works concurrently with the processor, peting for individual memory bus cycles to input/output successive words of a data block. If the I/O speed is not very high, the memory accesses by the processor and the DMA controller can be interwoven. Time is accrued on a cyclebycycle basis. Neither the processor nor the DMA controller can continuously use all the memory bus cycles during any time interval. This operational mode of the DMA controller is called cycle stealing, so named because the I/O subsystem is essentially “stealing” memory bus cycles from the processor. This mode integrates the DMA memory accesses into CPU activity and avoids serious disruption of the main processing. Alternatively, for even higher I/O transfer speed, DMA operations require bus time, which can be allocated in block of cycles known as bursts. During a burst of memory cycles, the processor is totally excluded from accessing memory. The DMA controller is given exclusive access to main memory and continuously inputs/outputs blocks of data at a speed parable to the memory speed. This operational mode of the DMA controller is called the block or burst mode. A DMA controller designed for this mode of operation usually incorporates a data storage buffer with a capacity matching the size of at least one data block. When the DMA controller utilizes the memory bus, it can transfer a data block directly between its data storage buffer and main memory. The following registers are necessary for the DMA to transfer a block of data: ● Data buffer register (DBR) － it can be implemented as two registers, one for input and the other for output, or even a set of registers prising a data storage buffer. ● DMA address register (DAR) － used to store the starting address of the memory buffer area where the block of data is to be read or written. ● Word counter (WC) － the contents specify the number of words in the block of data remaining to be transferred and it is automatically decremented after each word is transferred. ● Control/status register (CSR) － used by the processor to send control information to the DMA controller and to collect the statuses and error information of the DMA controller and the I/O devices attached to it. Using these registers, the DMA controller knows the addresses of the source and destination data blocks, as well as the quantity of data to be transferred. Once the DMA controller acquires the memory bus, the block transfer operati。